From: Michael Walle <mwalle@kernel.org>
To: Peter Robinson <pbrobinson@gmail.com>
Cc: Jagan Teki <jagan@amarulasolutions.com>,
Tom Rini <trini@konsulko.com>, Simon Glass <sjg@chromium.org>,
Andre Przywara <andre.przywara@arm.com>,
u-boot@lists.denx.de
Subject: Re: [PATCH 0/2] spi: sunxi: Improve the loading speed
Date: Fri, 12 Jul 2024 20:11:05 +0200 [thread overview]
Message-ID: <2a736c4e1191d61953a74fa9e3776388@kernel.org> (raw)
In-Reply-To: <CALeDE9P05YN092mYQ15Kha+1sd6Yp97qkk-ODMyXASB2Ae_SVQ@mail.gmail.com>
>> Right now, the maximal transfer speed from an SPI flash on a V3s is
>> about 240kb/s. That is pretty slow. It turns out, that due to an
>> error u-boot is setting the maximum frequency to 1MHz. By fixing
>> that another bug is unearthed: one cannot set a clock divider of 1:1
>> due to the handling between CDR1 and CDR2 handling. By fixing that
>> I achieved loading speeds of about 1.5MB/s.
>
> Minor nit, should the clock fix go first so there's not a regression
> if someone needs to do a bisect on the first commit?
Sure can do for the next version.
-michael
next prev parent reply other threads:[~2024-07-12 18:11 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-12 17:14 [PATCH 0/2] spi: sunxi: Improve the loading speed Michael Walle
2024-07-12 17:14 ` [PATCH 1/2] spi: sunxi: drop max_hz handling Michael Walle
2024-07-16 0:05 ` Andre Przywara
2024-07-16 6:58 ` Michael Walle
2024-07-16 14:20 ` Andre Przywara
2024-07-12 17:14 ` [PATCH 2/2] spi: sunxi: fix clock divider calculation for max frequency setting Michael Walle
2024-07-16 0:39 ` Andre Przywara
2024-07-16 7:18 ` Michael Walle
2024-07-12 17:28 ` [PATCH 0/2] spi: sunxi: Improve the loading speed Peter Robinson
2024-07-12 18:11 ` Michael Walle [this message]
2024-07-16 0:32 ` Andre Przywara
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