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dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=kishon@ti.com Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 169EW7aH029230; Fri, 9 Jul 2021 09:32:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1625841127; bh=QXCn9eoliLlsV9hdmFhJPFozfmzBOW89yTMcpUNMcoI=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=DrwpH0gbIIaQS1KitrHOLtpvtcQrceRHQc9SCWathy0bbjK+cJ/cdfqdsPwjvLOC0 TE2WoDj7o9FcfRPT37s9pQ6Ibz6ewZ2CF+uDkLXSaJakPoTbhiLjZv6aYki8+J1Xq2 ZHjqt87E+vvi4bclbk9ve3+vFdoJdvFjHuhpqR58= Received: from DFLE109.ent.ti.com (dfle109.ent.ti.com [10.64.6.30]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 169EW6H2071104 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 9 Jul 2021 09:32:07 -0500 Received: from DFLE111.ent.ti.com (10.64.6.32) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2; Fri, 9 Jul 2021 09:32:06 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2176.2 via Frontend Transport; Fri, 9 Jul 2021 09:32:06 -0500 Received: from [10.250.234.184] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 169EW45B109175; Fri, 9 Jul 2021 09:32:04 -0500 Subject: Re: [PATCH v3 19/20] env: ti: j721e-evm: Add env variable to power on & reset QSGMII PHY in J7200 EVM To: Tom Rini CC: Lokesh Vutla , Simon Glass , , , References: <20210504104155.19222-1-kishon@ti.com> <20210504104155.19222-20-kishon@ti.com> <20210507171452.GT17669@bill-the-cat> <897775d4-c7f2-0159-33c7-9b152b149cba@ti.com> <20210511143311.GP17669@bill-the-cat> From: Kishon Vijay Abraham I Message-ID: <2af86da3-e47a-b142-efb4-46fde4c0e443@ti.com> Date: Fri, 9 Jul 2021 20:02:03 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20210511143311.GP17669@bill-the-cat> Content-Type: text/plain; charset="windows-1252" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Tom, On 11/05/21 8:03 pm, Tom Rini wrote: > On Tue, May 11, 2021 at 07:28:10PM +0530, Kishon Vijay Abraham I wrote: >> Hi Tom, >> >> On 07/05/21 10:44 pm, Tom Rini wrote: >>> On Tue, May 04, 2021 at 04:11:54PM +0530, Kishon Vijay Abraham I wrote: >>> >>>> MAIN CPSW0 requires the PHY to be powered on and reset for QSGMII >>>> operation. Add a env variable to configure driving "0" on ENET_EXP_PWRDN >>>> controlled by GPIO EXPANDER2 (I2C Addr: 0x22), PIN: 17 and driving "1" >>>> on ENET_EXP_RESETZ controlled by GPIO EXPANDER2 (I2C Addr: 0x22), >>>> PIN: 18. >>>> >>>> Signed-off-by: Kishon Vijay Abraham I >>>> Reviewed-by: Suman Anna >>>> --- >>>> include/configs/j721e_evm.h | 16 +++++++++++++++- >>>> 1 file changed, 15 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/include/configs/j721e_evm.h b/include/configs/j721e_evm.h >>>> index b707fc4e89..00d0a18a68 100644 >>>> --- a/include/configs/j721e_evm.h >>>> +++ b/include/configs/j721e_evm.h >>>> @@ -139,11 +139,24 @@ >>>> #endif /* CONFIG_TARGET_J721E_A72_EVM */ >>>> >>>> #ifdef CONFIG_TARGET_J7200_A72_EVM >>>> +#define EXTRA_ENV_CONFIG_MAIN_CPSW0_QSGMII_PHY \ >>>> + "do_main_cpsw0_qsgmii_phyinit=1\0" \ >>> >>> When would this be not true? >> >> If the user don't want to use QSGMII, this could be set to false. For >> instance the SERDES in J7200 can be used such that it can be used with >> two protocols at a time. So it can be either PCIe + QSGMII or PCIe + >> USB. So for use cases which require PCIe + USB, this could be set to false. > > Then we need to create doc/board/ti/j721e_evm.rst with some general > content and then document the above in there. There is already a document @ board/ti/j721e/README which has some general information. Maybe that could be updated and moved to doc/board/ti/j721e_evm.rst? Thanks Kishon > >>>> + "init_main_cpsw0_qsgmii_phy=gpio set gpio@22_17;" \ >>>> + "gpio clear gpio@22_16\0" \ >>>> + "main_cpsw0_qsgmii_phyinit=" \ >>>> + "if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1 && test ${dorprocboot} -eq 1 && " \ >>>> + "test ${boot} = mmc; then " \ >>> >>> And why only on mmc? >> >> The current J7200 u-boot code loads firmwares for remote cores only from >> MMC. So if it's not mmc, it's not going to load ethernet firmware and >> hence not required to configure the PHY. > > OK. Please make sure this is also part of the documentation. Thanks. >