[U-Boot] [PATCH v2 1/9] sunxi: initial sun7i clocks and timer support.

Marek Vasut
2014-03-24T20:52:38Z

On Friday, March 21, 2014 at 10:54:18 PM, Ian Campbell wrote:
> This has been stripped back for mainlining and supports only sun7i. These
> changes are not useful by themselves but are split out to make the patch
> sizes more manageable.

[...]

> +int clock_init(void)
> +{
> + struct sunxi_ccm_reg *const ccm =
> + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> +
> +#ifdef CONFIG_SPL_BUILD
> + clock_init_safe();
> +#endif
> +
> + /* uart clock source is apb1 */
> + sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M);
> + sr32(&ccm->apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N);
> + sr32(&ccm->apb1_clk_div_cfg, 0, 5, APB1_FACTOR_M);

sr32() is not defined anywhere.

> + /* open the clock for uart */
> + sr32(&ccm->apb1_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN);
> +
> + return 0;
> +}
> +
> +/* Return PLL5 frequency in Hz
> + * Note: Assumes PLL5 reference is 24MHz clock
> + */
> +unsigned int clock_get_pll5(void)
> +{
> + struct sunxi_ccm_reg *const ccm =
> + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
> + uint32_t rval = readl(&ccm->pll5_cfg);
> + int n = (rval >> 8) & 0x1f;
> + int k = ((rval >> 4) & 3) + 1;
> + int p = 1 << ((rval >> 16) & 3);
> + return 24000000 * n * k / p;

Please fix the magic values here.
[...]

> +#ifdef CONFIG_SPL_BUILD
> +#define PLL1_CFG(N, K, M, P) (1 << 31 | 0 << 30 | 8 << 26 | 0 << 25 |
\
> + 16 << 20 | (P) << 16 | 2 << 13 | (N) << 8 | \
> + (K) << 4 | 0 << 3 | 0 << 2 | (M) << 0)

Here is well.

> +#define RDIV(a, b) ((a + (b) - 1) / (b))

This is some kind of DIV_ROUND_UP() from include/common.h ?

[...]

> + /* Map divisors to register values */
> + axi = axi - 1;
> + if (ahb > 4)
> + ahb = 3;
> + else if (ahb > 2)
> + ahb = 2;
> + else if (ahb > 1)
> + ahb = 1;
> + else
> + ahb = 0;
> +
> + apb0 = apb0 - 1;
> +
> + /* Switch to 24MHz clock while changing PLL1 */
> + writel(AXI_DIV_1 << AXI_DIV_SHIFT |
> + AHB_DIV_2 << AHB_DIV_SHIFT |
> + APB0_DIV_1 << APB0_DIV_SHIFT |
> + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
> + &ccm->cpu_ahb_apb0_cfg);
> + sdelay(20);

What is sdelay() function all about ?

[...]

> +static struct sunxi_timer *timer_base =
> + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->timer[TIMER_NUM];
> +
> +/* macro to read the 32 bit timer: since it decrements, we invert read
> value */ +#define READ_TIMER() (~readl(&timer_base->val))

This macro has to go, just use ~readl() in place. But still, why do you use that
negation in "~readl()" anyway ? …