From: DarkKhan <muratkarahan@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] P2020 L2 cache as SRAM
Date: Wed, 19 Oct 2011 04:53:05 -0700 (PDT) [thread overview]
Message-ID: <32681721.post@talk.nabble.com> (raw)
In-Reply-To: <20110119140221.083392bf@udp111988uds.am.freescale.net>
Hi Scott,
I need your help with an issue ,i think, related to this topic.
I have P2020RDB development kit and try to boot it from nand flash using
u-boot codes.
But unfortunately, nand boot process is trapped. Once i have changed the
value of the CONFIG_SYS_INIT_L2_ADDR definition from F8F80000 to the
F7F80000, than that problem has been disappeared. Why ?! Any idea ?
Also i wonder, why this CONFIG_SYS_INIT_L2_ADDR is chosen as F8F80000 for
the L2 SRAM base adress through the u-boot codes.
Those codes can be found form those links below:
http://gitorious.org/beagleboard-validation/u-boot/blobs/f51cdaf19141151ce2b40d562a468605340f2315/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
(=> Line number 48)
http://gitorious.org/beagleboard-validation/u-boot/blobs/525f6c3add71c0fba0911d770bba5e9282be0cf2/include/configs/P1_P2_RDB.h
(=> Line number 106)
I couldn't undertand why f8f80000 address is chosen for L2 SRAM base
adress in the the u-boot P1_P2_RDB.h header file?
thnx for
your
attention.
-murat
Scott Wood-2 wrote:
>
> On Wed, 19 Jan 2011 08:50:52 +0100
> Fabian Cenedese <Cenedese@indel.ch> wrote:
>
>> At 09:07 17.01.2011 +0100, Fabian Cenedese wrote:
>> >Hi
>> >
>> >We're trying to configure the PPC P2020 cpu to use the L2 cache
>> >as SRAM so we can load the U-Boot code in there. However we
>> >stumble into problems. Sometimes the cpu goes on trap when
>> >trying to access this area. Sometimes there's no trap but we
>> >seem to access a different area. That's probably a problem with
>> >setting up a TLB/LAW.
>> >
>> >Has anybody already done this and could share some code with
>> >us?
>> >
>> >I've seen that there's a mpc85xx branch with quite some work
>> >going on. Where should we base our work on? Should we use
>> >the master or is it better to use this branch? I'm used to svn,
>> >not git, so there may be other options I don't know about yet.
>>
>> I know you're busy with patches and releasing, I just wanted
>> to ask again if anybody has already done this.
>
> Yes, it's been done. P1_P2_RDB does this when configured for NAND boot.
>
> Look for CONFIG_SYS_INIT_L2_ADDR.
>
> -Scott
>
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
>
--
View this message in context: http://old.nabble.com/-U-Boot--P2020-L2-cache-as-SRAM-tp30688713p32681721.html
Sent from the Uboot - Users mailing list archive at Nabble.com.
next prev parent reply other threads:[~2011-10-19 11:53 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-01-17 8:07 [U-Boot] P2020 L2 cache as SRAM Fabian Cenedese
2011-01-19 7:50 ` Fabian Cenedese
2011-01-19 20:02 ` Scott Wood
2011-01-20 9:21 ` Fabian Cenedese
2011-10-19 11:53 ` DarkKhan [this message]
2011-10-19 12:12 ` Aggrwal Poonam-B10812
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=32681721.post@talk.nabble.com \
--to=muratkarahan@gmail.com \
--cc=u-boot@lists.denx.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox