From mboxrd@z Thu Jan 1 00:00:00 1970 From: DarkKhan Date: Wed, 19 Oct 2011 04:53:05 -0700 (PDT) Subject: [U-Boot] P2020 L2 cache as SRAM In-Reply-To: <20110119140221.083392bf@udp111988uds.am.freescale.net> References: <5.2.0.9.1.20110117090223.049fede8@localhost> <5.2.0.9.1.20110119084938.049e7cb8@localhost> <20110119140221.083392bf@udp111988uds.am.freescale.net> Message-ID: <32681721.post@talk.nabble.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Scott, I need your help with an issue ,i think, related to this topic. I have P2020RDB development kit and try to boot it from nand flash using u-boot codes. But unfortunately, nand boot process is trapped. Once i have changed the value of the CONFIG_SYS_INIT_L2_ADDR definition from F8F80000 to the F7F80000, than that problem has been disappeared. Why ?! Any idea ? Also i wonder, why this CONFIG_SYS_INIT_L2_ADDR is chosen as F8F80000 for the L2 SRAM base adress through the u-boot codes. Those codes can be found form those links below: http://gitorious.org/beagleboard-validation/u-boot/blobs/f51cdaf19141151ce2b40d562a468605340f2315/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c (=> Line number 48) http://gitorious.org/beagleboard-validation/u-boot/blobs/525f6c3add71c0fba0911d770bba5e9282be0cf2/include/configs/P1_P2_RDB.h (=> Line number 106) I couldn't undertand why f8f80000 address is chosen for L2 SRAM base adress in the the u-boot P1_P2_RDB.h header file? thnx for your attention. -murat Scott Wood-2 wrote: > > On Wed, 19 Jan 2011 08:50:52 +0100 > Fabian Cenedese wrote: > >> At 09:07 17.01.2011 +0100, Fabian Cenedese wrote: >> >Hi >> > >> >We're trying to configure the PPC P2020 cpu to use the L2 cache >> >as SRAM so we can load the U-Boot code in there. However we >> >stumble into problems. Sometimes the cpu goes on trap when >> >trying to access this area. Sometimes there's no trap but we >> >seem to access a different area. That's probably a problem with >> >setting up a TLB/LAW. >> > >> >Has anybody already done this and could share some code with >> >us? >> > >> >I've seen that there's a mpc85xx branch with quite some work >> >going on. Where should we base our work on? Should we use >> >the master or is it better to use this branch? I'm used to svn, >> >not git, so there may be other options I don't know about yet. >> >> I know you're busy with patches and releasing, I just wanted >> to ask again if anybody has already done this. > > Yes, it's been done. P1_P2_RDB does this when configured for NAND boot. > > Look for CONFIG_SYS_INIT_L2_ADDR. > > -Scott > > _______________________________________________ > U-Boot mailing list > U-Boot at lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > > -- View this message in context: http://old.nabble.com/-U-Boot--P2020-L2-cache-as-SRAM-tp30688713p32681721.html Sent from the Uboot - Users mailing list archive at Nabble.com.