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[86.58.6.171]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43d43f55c3dsm135978805e9.23.2025.03.23.05.18.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Mar 2025 05:18:18 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Tom Rini , Andre Przywara Cc: Simon Glass , Mikhail Kalashnikov , u-boot@lists.denx.de, linux-sunxi@lists.linux.dev, Lukasz Majewski , Sean Anderson Subject: Re: [PATCH 16/34] clk: sunxi: Add support for the A523 -R CCU Date: Sun, 23 Mar 2025 13:18:17 +0100 Message-ID: <3340159.aeNJFYEL58@jernej-laptop> In-Reply-To: <20250323113544.7933-17-andre.przywara@arm.com> References: <20250323113544.7933-1-andre.przywara@arm.com> <20250323113544.7933-17-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Dne nedelja, 23. marec 2025 ob 12:35:26 Srednjeevropski standardni =C4=8Das= je Andre Przywara napisal(a): > Add a clock driver for the PRCM clock controller on the Allwinner A523 > family of SoCs, often also used with an "r" prefix or suffix. > This just describes the clock gates and reset lines for the few devices > that we would need, most prominently the R_I2C device for the PMIC. >=20 > Signed-off-by: Andre Przywara > --- > drivers/clk/sunxi/Kconfig | 7 ++++++ > drivers/clk/sunxi/Makefile | 1 + > drivers/clk/sunxi/clk_a523_r.c | 44 ++++++++++++++++++++++++++++++++++ > drivers/clk/sunxi/clk_sunxi.c | 5 ++++ > 4 files changed, 57 insertions(+) > create mode 100644 drivers/clk/sunxi/clk_a523_r.c >=20 > diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig > index 74e89b86301..1c1cc82719c 100644 > --- a/drivers/clk/sunxi/Kconfig > +++ b/drivers/clk/sunxi/Kconfig > @@ -136,4 +136,11 @@ config CLK_SUN55I_A523 > This enables common clock driver support for platforms based > on Allwinner A523/T527 SoC. > =20 > +config CLK_SUN55I_A523_R > + bool "Clock driver for Allwinner A523 generation PRCM" > + default MACH_SUN55I_A523 > + help > + This enables common clock driver support for the PRCM > + in Allwinner A523/T527 SoCs. > + > endif # CLK_SUNXI > diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile > index dd33eabe2ed..93b542cebcd 100644 > --- a/drivers/clk/sunxi/Makefile > +++ b/drivers/clk/sunxi/Makefile > @@ -26,3 +26,4 @@ obj-$(CONFIG_CLK_SUN50I_H616) +=3D clk_h616.o > obj-$(CONFIG_CLK_SUN50I_A64) +=3D clk_a64.o > obj-$(CONFIG_CLK_SUN50I_A100) +=3D clk_a100.o > obj-$(CONFIG_CLK_SUN55I_A523) +=3D clk_a523.o > +obj-$(CONFIG_CLK_SUN55I_A523_R) +=3D clk_a523_r.o > diff --git a/drivers/clk/sunxi/clk_a523_r.c b/drivers/clk/sunxi/clk_a523_= r.c > new file mode 100644 > index 00000000000..e864ce16199 > --- /dev/null > +++ b/drivers/clk/sunxi/clk_a523_r.c > @@ -0,0 +1,44 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (C) 2024 Arm Ltd. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +static struct ccu_clk_gate a523_r_gates[] =3D { > + [CLK_R_AHB] =3D GATE_DUMMY, > + [CLK_R_APB0] =3D GATE_DUMMY, > + [CLK_R_APB1] =3D GATE_DUMMY, > + [CLK_BUS_R_TWD] =3D GATE(0x12c, BIT(0)), > + [CLK_BUS_R_I2C0] =3D GATE(0x19c, BIT(0)), > + [CLK_BUS_R_I2C1] =3D GATE(0x19c, BIT(1)), > + [CLK_BUS_R_I2C2] =3D GATE(0x19c, BIT(2)), > + [CLK_BUS_R_RTC] =3D GATE(0x20c, BIT(0)), > +}; > + > +static struct ccu_reset a523_r_resets[] =3D { > +// [RST_BUS_R_TIMER] =3D RESET(0x11c, BIT(16)), > + [RST_BUS_R_TWD] =3D RESET(0x12c, BIT(16)), > +// [RST_BUS_R_PWMCTRL] =3D RESET(0x13c, BIT(16)), > +// [RST_BUS_R_SPI] =3D RESET(0x15c, BIT(16)), > +// [RST_BUS_R_UART0] =3D RESET(0x18c, BIT(16)), > +// [RST_BUS_R_UART1] =3D RESET(0x18c, BIT(17)), > + [RST_BUS_R_I2C0] =3D RESET(0x19c, BIT(16)), > + [RST_BUS_R_I2C1] =3D RESET(0x19c, BIT(17)), > + [RST_BUS_R_I2C2] =3D RESET(0x19c, BIT(18)), > +// [RST_BUS_R_PPU1] =3D RESET(0x1ac, BIT(17)), > + [RST_BUS_R_RTC] =3D RESET(0x20c, BIT(16)), > +// [RST_BUS_R_CPUCFG] =3D RESET(0x22c, BIT(16)), Any specific reason that you commented out some reset lines? Best regards, Jernej > +}; > + > +const struct ccu_desc a523_r_ccu_desc =3D { > + .gates =3D a523_r_gates, > + .resets =3D a523_r_resets, > + .num_gates =3D ARRAY_SIZE(a523_r_gates), > + .num_resets =3D ARRAY_SIZE(a523_r_resets), > +}; > diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c > index 30baabaafcd..842a0541bd6 100644 > --- a/drivers/clk/sunxi/clk_sunxi.c > +++ b/drivers/clk/sunxi/clk_sunxi.c > @@ -127,6 +127,7 @@ extern const struct ccu_desc h6_r_ccu_desc; > extern const struct ccu_desc r40_ccu_desc; > extern const struct ccu_desc v3s_ccu_desc; > extern const struct ccu_desc a523_ccu_desc; > +extern const struct ccu_desc a523_r_ccu_desc; > =20 > static const struct udevice_id sunxi_clk_ids[] =3D { > #ifdef CONFIG_CLK_SUN4I_A10 > @@ -228,6 +229,10 @@ static const struct udevice_id sunxi_clk_ids[] =3D { > #ifdef CONFIG_CLK_SUN55I_A523 > { .compatible =3D "allwinner,sun55i-a523-ccu", > .data =3D (ulong)&a523_ccu_desc }, > +#endif > +#ifdef CONFIG_CLK_SUN55I_A523_R > + { .compatible =3D "allwinner,sun55i-a523-r-ccu", > + .data =3D (ulong)&a523_r_ccu_desc }, > #endif > { } > }; >=20