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[46.142.60.212]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-39c30096b9csm12310734f8f.13.2025.04.07.07.27.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Apr 2025 07:27:56 -0700 (PDT) Message-ID: <353d3a52-d101-4938-9f8d-2b8db3ca9b87@linaro.org> Date: Mon, 7 Apr 2025 16:27:55 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/5] clk/qcom: apq8096: fix the sdhci clock To: Jorge Ramirez , neil.armstrong@linaro.org Cc: sumit.garg@kernel.org, u-boot-qcom@groups.io, u-boot@lists.denx.de References: <20250407120536.236003-1-jorge.ramirez@oss.qualcomm.com> <20250407120536.236003-3-jorge.ramirez@oss.qualcomm.com> Content-Language: en-US From: Caleb Connolly In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On 4/7/25 16:17, Jorge Ramirez wrote: > On 07/04/25 14:36:51, neil.armstrong@linaro.org wrote: >> On 07/04/2025 14:05, Jorge Ramirez-Ortiz wrote: >>> Select the right clock for sdhci. >>> >>> Signed-off-by: Jorge Ramirez-Ortiz >>> Reviewed-by: Neil Armstrong >>> --- >>> drivers/clk/qcom/clock-apq8096.c | 2 +- >>> 1 file changed, 1 insertion(+), 1 deletion(-) >>> >>> diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c >>> index bc00826a5e8..551f52d5197 100644 >>> --- a/drivers/clk/qcom/clock-apq8096.c >>> +++ b/drivers/clk/qcom/clock-apq8096.c >>> @@ -83,7 +83,7 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate) >>> struct msm_clk_priv *priv = dev_get_priv(clk->dev); >>> switch (clk->id) { >>> - case GCC_SDCC1_APPS_CLK: /* SDC1 */ >>> + case GCC_SDCC2_APPS_CLK: /* SDC2 */ >> >> Should be GCC_SDCC2_AHB_CLK > > why? also if I do that, mcc fails to probe GCC_SDCC2_APPS_CLK is correct, that's the "core" clock and the one the sdhci_msm driver calls clk_set_rate() on. So this patch is good. I suspect the misuse of GCC_SDCC1_APPS_CLK is from way back when this board had a custom DT that didn't follow upstream. Reviewed-by: Caleb Connolly > >> >>> return clk_init_sdc(priv, rate); >>> break; >>> case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/ >> -- Caleb (they/them)