From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dinh Nguyen Date: Thu, 8 Mar 2018 15:44:27 -0600 Subject: [U-Boot] [PATCH] arm: socfpga: gen5: Enabling cache and TLB maintenance broadcast In-Reply-To: <1520517675.2582.11.camel@intel.com> References: <1519794775-29948-1-git-send-email-chin.liang.see@intel.com> <031aa15c-7c15-0a75-acf9-108d1de3fd5f@denx.de> <1520517675.2582.11.camel@intel.com> Message-ID: <367297fb-1224-5b7d-44bd-e3540704c666@kernel.org> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de On 03/08/2018 08:01 AM, See, Chin Liang wrote: > On Thu, 2018-03-01 at 17:17 +0100, Marek Vasut wrote: >> On 02/28/2018 06:12 AM, chin.liang.see at intel.com wrote: >>> >>> From: Chin Liang See >>> >>> Enabling cache and TLB maintenance broadcast through ACTLR as >>> required >>> by Linux. >> This needs far more clarification. What is the problem you're fixing >> here ? How does it fix the problem ? > > Sure. When the 2 processors is enabled with SMP, popen operation would > fail as content are different after the copy. This issue goes away when > we force Linux to run with 1 core only. Checked with ARM, this bit is > required by Linux when running SMP. > What's a "popen" operation? Shouldn't you also set the SMP along with the FW bit? Dinh