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Tue, 11 Nov 2025 02:29:30 -0800 (PST) Received: from [192.168.0.39] ([82.76.24.202]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4778164b7fdsm17154125e9.3.2025.11.11.02.29.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 11 Nov 2025 02:29:30 -0800 (PST) Message-ID: <36ad560d-48d6-4ffb-bcde-b031bdcc3f33@linaro.org> Date: Tue, 11 Nov 2025 12:29:29 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] mtd: rawnand: atmel: set pmecc data setup time To: Zixun LI , Dario Binacchi , u-boot@lists.denx.de, Michael Trimarchi , Tom Rini , Balamanikandan Gunasundar References: <20251106-pmecc-v1-0-a1f3cf430be9@hifiphile.com> <20251106-pmecc-v1-1-a1f3cf430be9@hifiphile.com> <20251107-condone-percolate-51ec103f3ef4@thorsis.com> From: Eugen Hristev Content-Language: en-US In-Reply-To: <20251107-condone-percolate-51ec103f3ef4@thorsis.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On 11/7/25 13:01, Alexander Dahl wrote: > Hello Eugen, > > Am Fri, Nov 07, 2025 at 12:52:05PM +0200 schrieb Eugen Hristev: >> Hello Zixun, Alexander, >> >> On 11/6/25 13:12, Zixun LI wrote: >>> Setup the pmecc data setup time as 3 clock cycles for 133MHz as >>> recommended by the datasheet. >>> >>> Backported from Linux: f552a7c7 ("mtd: rawnand: atmel: set pmecc data >>> setup time") >> >> Maybe use 12 digits commit hash ? I cannot find this commit in Linux > > v6.16-rc4-10-gf552a7c7e0a14 aka > f552a7c7e0a14215cb8a6fd89e60fa3932a74786 from July 2025. > >> >>> >>> Fixes: a490e1b7c017c ("nand: atmel: Add pmecc driver") >>> >>> Signed-off-by: Zixun LI >>> --- >>> drivers/mtd/nand/raw/atmel/pmecc.c | 6 ++++++ >>> 1 file changed, 6 insertions(+) >>> >>> diff --git a/drivers/mtd/nand/raw/atmel/pmecc.c b/drivers/mtd/nand/raw/atmel/pmecc.c >>> index e500a0fe3f8671ff08195c94c3383696a7731eb3..7c4e9bd5f9967b119239adf2b39e683ea62b71fd 100644 >>> --- a/drivers/mtd/nand/raw/atmel/pmecc.c >>> +++ b/drivers/mtd/nand/raw/atmel/pmecc.c >>> @@ -142,6 +142,7 @@ struct atmel_pmecc_caps { >>> int nstrengths; >>> int el_offset; >>> bool correct_erased_chunks; >>> + bool clk_ctrl; >>> }; >>> >>> struct atmel_pmecc_user_conf_cache { >>> @@ -840,6 +841,10 @@ atmel_pmecc_create(struct udevice *dev, >>> >>> pmecc->regs.timing = 0; >>> >>> + /* pmecc data setup time */ >>> + if (caps->clk_ctrl) >>> + writel(PMECC_CLK_133MHZ, pmecc->regs.base + ATMEL_PMECC_CLK); >>> + >>> /* Disable all interrupts before registering the PMECC handler. */ >>> writel(0xffffffff, pmecc->regs.base + ATMEL_PMECC_IDR); >>> atmel_pmecc_reset(pmecc); >>> @@ -884,6 +889,7 @@ static struct atmel_pmecc_caps at91sam9g45_caps = { >>> .strengths = atmel_pmecc_strengths, >>> .nstrengths = 5, >>> .el_offset = 0x8c, >>> + .clk_ctrl = true, >> >> This appears to be done only for sam9g45. >> >> So, Alexander, this should not impact sam9x60 . > > Yes it should. According to arch/arm/boot/dts/microchip/sam9x60.dtsi > the compatible used on sam9x60 is "atmel,at91sam9g45-pmecc", see: > > pmecc: ecc-engine@ffffe000 { > compatible = "microchip,sam9x60-pmecc", "atmel,at91sam9g45-pmecc"; > reg = <0xffffe000 0x300>, > <0xffffe600 0x100>; > }; > Yes it looks you are right. sam9x60 does not have a dedicated caps but reusing the sam9g45 one, and I missed that. Thanks >> I looked a bit in the Linux driver and this appears to be just as bad: >> 133 Mhz clock config hardcoded. I would expect this clock to be taken >> from a clock input and not hardcoded. But oh well, if this clock is to >> be changed in another device, it would be exposed somewhere... > > I did not look into that deeply, but if it is like you said, someone > should. This sounds bad. > > Greets > Alex > >> >> Eugen >> >>> }; >>> >>> static struct atmel_pmecc_caps sama5d4_caps = { >>> >>