From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DE12BC43334 for ; Mon, 18 Jul 2022 10:28:59 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id C8D00839F6; Mon, 18 Jul 2022 12:28:57 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1658140138; bh=sWqs3ax8wTzylZatVrZQ5yllwIHaoAd3KEiHcuaGqng=; h=Date:Subject:To:Cc:References:From:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=Q/+DEh6XYvt7oGvl42q49xJK9+CItdUP9y6+jcMk0y74iE57v/OMGAALUBKWZ26nE uRjwsNMcIuV8PKmeNl7iszC8ohDg8AbhtAlcwr7w5nmaqpam1+zhh78IWcEa0UlfL4 W2ga6ixboUM8VKBSFa9BFe40QvMqBH0L3UTkVuhi9ZUjoUcaFVJ0OJ/L/gf39vqrmR 48PG+Yy5bQoeYR49uI7kE3mYDkV1o5Np4g4x0dCv+zggF5CqCwONYjjHrRTeHoM98b u/gvM5JKQZfySH7SQ0f9TniIcGt/MtWMDKEW2IdfSQ5THoq9I9CFCxJDGBnSdmVg1o 0Izr9muL0nO1w== Received: by phobos.denx.de (Postfix, from userid 109) id 3541483E60; Mon, 18 Jul 2022 12:28:56 +0200 (CEST) Received: from mout-u-204.mailbox.org (mout-u-204.mailbox.org [80.241.59.204]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id D6ABE8118A for ; Mon, 18 Jul 2022 12:28:53 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp202.mailbox.org (smtp202.mailbox.org [10.196.197.202]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-204.mailbox.org (Postfix) with ESMTPS id 4LmdVC72rQz9sSf; Mon, 18 Jul 2022 12:28:51 +0200 (CEST) Message-ID: <37041d6b-519d-2d8a-77c5-c19cff3c5130@denx.de> Date: Mon, 18 Jul 2022 12:28:51 +0200 MIME-Version: 1.0 Subject: Re: [PATCH] arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times Content-Language: en-US To: =?UTF-8?Q?Pali_Roh=c3=a1r?= , =?UTF-8?Q?Marek_Beh=c3=ban?= , Chris Packham Cc: u-boot@lists.denx.de References: <20220715081312.19369-1-pali@kernel.org> From: Stefan Roese In-Reply-To: <20220715081312.19369-1-pali@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean On 15.07.22 10:13, Pali Rohár wrote: > Change detection of platform/cpu from runtime to compile time via config > define. This completely eliminates compiling code which is not going to run > on selected platform. Code which parses and prints device / revision id > still reads device id from MVEBU_REG_PCIE_DEVID register, but only once. > > Signed-off-by: Pali Rohár Reviewed-by: Stefan Roese Thanks, Stefan > --- > arch/arm/mach-mvebu/cpu.c | 67 ++++++++++---------------- > arch/arm/mach-mvebu/dram.c | 18 +++---- > arch/arm/mach-mvebu/include/mach/cpu.h | 9 ---- > 3 files changed, 32 insertions(+), 62 deletions(-) > > diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c > index 173d95a760a3..1457af1d6aa3 100644 > --- a/arch/arm/mach-mvebu/cpu.c > +++ b/arch/arm/mach-mvebu/cpu.c > @@ -54,33 +54,6 @@ void reset_cpu(void) > ; > } > > -int mvebu_soc_family(void) > -{ > - u16 devid = (readl(MVEBU_REG_PCIE_DEVID) >> 16) & 0xffff; > - > - switch (devid) { > - case SOC_MV78230_ID: > - case SOC_MV78260_ID: > - case SOC_MV78460_ID: > - return MVEBU_SOC_AXP; > - > - case SOC_88F6720_ID: > - return MVEBU_SOC_A375; > - > - case SOC_88F6810_ID: > - case SOC_88F6820_ID: > - case SOC_88F6828_ID: > - return MVEBU_SOC_A38X; > - > - case SOC_98DX3236_ID: > - case SOC_98DX3336_ID: > - case SOC_98DX4251_ID: > - return MVEBU_SOC_MSYS; > - } > - > - return MVEBU_SOC_UNKNOWN; > -} > - > u32 get_boot_device(void) > { > u32 val; > @@ -305,7 +278,10 @@ int print_cpuinfo(void) > break; > } > > - if (mvebu_soc_family() == MVEBU_SOC_AXP) { > + switch (devid) { > + case SOC_MV78230_ID: > + case SOC_MV78260_ID: > + case SOC_MV78460_ID: > switch (revid) { > case 1: > puts("A0"); > @@ -317,9 +293,9 @@ int print_cpuinfo(void) > printf("?? (%x)", revid); > break; > } > - } > + break; > > - if (mvebu_soc_family() == MVEBU_SOC_A375) { > + case SOC_88F6720_ID: > switch (revid) { > case MV_88F67XX_A0_ID: > puts("A0"); > @@ -328,9 +304,11 @@ int print_cpuinfo(void) > printf("?? (%x)", revid); > break; > } > - } > + break; > > - if (mvebu_soc_family() == MVEBU_SOC_A38X) { > + case SOC_88F6810_ID: > + case SOC_88F6820_ID: > + case SOC_88F6828_ID: > switch (revid) { > case MV_88F68XX_Z1_ID: > puts("Z1"); > @@ -345,9 +323,11 @@ int print_cpuinfo(void) > printf("?? (%x)", revid); > break; > } > - } > + break; > > - if (mvebu_soc_family() == MVEBU_SOC_MSYS) { > + case SOC_98DX3236_ID: > + case SOC_98DX3336_ID: > + case SOC_98DX4251_ID: > switch (revid) { > case 3: > puts("A0"); > @@ -359,6 +339,11 @@ int print_cpuinfo(void) > printf("?? (%x)", revid); > break; > } > + break; > + > + default: > + printf("?? (%x)", revid); > + break; > } > > get_sar_freq(&sar_freq); > @@ -463,7 +448,7 @@ int arch_cpu_init(void) > struct pl310_regs *const pl310 = > (struct pl310_regs *)CONFIG_SYS_PL310_BASE; > > - if (mvebu_soc_family() == MVEBU_SOC_A38X) { > + if (IS_ENABLED(CONFIG_ARMADA_38X)) { > /* > * To fully release / unlock this area from cache, we need > * to flush all caches and disable the L2 cache. > @@ -492,7 +477,7 @@ int arch_cpu_init(void) > */ > mvebu_mbus_probe(NULL, 0); > > - if (mvebu_soc_family() == MVEBU_SOC_AXP) { > + if (IS_ENABLED(CONFIG_ARMADA_XP)) { > /* > * Now the SDRAM access windows can be reconfigured using > * the information in the SDRAM scratch pad registers > @@ -506,7 +491,7 @@ int arch_cpu_init(void) > */ > mvebu_mbus_probe(windows, ARRAY_SIZE(windows)); > > - if (mvebu_soc_family() == MVEBU_SOC_AXP) { > + if (IS_ENABLED(CONFIG_ARMADA_XP)) { > /* Enable GBE0, GBE1, LCD and NFC PUP */ > clrsetbits_le32(ARMADA_XP_PUP_ENABLE, 0, > GE0_PUP_EN | GE1_PUP_EN | LCD_PUP_EN | > @@ -530,9 +515,9 @@ u32 mvebu_get_nand_clock(void) > { > u32 reg; > > - if (mvebu_soc_family() == MVEBU_SOC_A38X) > + if (IS_ENABLED(CONFIG_ARMADA_38X)) > reg = MVEBU_DFX_DIV_CLK_CTRL(1); > - else if (mvebu_soc_family() == MVEBU_SOC_MSYS) > + else if (IS_ENABLED(CONFIG_ARMADA_MSYS)) > reg = MVEBU_DFX_DIV_CLK_CTRL(8); > else > reg = MVEBU_CORE_DIV_CLK_CTRL(1); > @@ -678,7 +663,7 @@ void enable_caches(void) > * ethernet driver (mvpp2). So lets keep the d-cache disabled > * until this is solved. > */ > - if (mvebu_soc_family() != MVEBU_SOC_A375) { > + if (IS_ENABLED(CONFIG_ARMADA_375)) { > /* Enable D-cache. I-cache is already enabled in start.S */ > dcache_enable(); > } > @@ -686,7 +671,7 @@ void enable_caches(void) > > void v7_outer_cache_enable(void) > { > - if (mvebu_soc_family() == MVEBU_SOC_AXP) { > + if (IS_ENABLED(CONFIG_ARMADA_XP)) { > struct pl310_regs *const pl310 = > (struct pl310_regs *)CONFIG_SYS_PL310_BASE; > u32 u; > diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c > index 349e0cc4c180..d398d0f7676a 100644 > --- a/arch/arm/mach-mvebu/dram.c > +++ b/arch/arm/mach-mvebu/dram.c > @@ -220,7 +220,7 @@ static int ecc_enabled(void) > return 0; > } > > -/* Return the width of the DRAM bus, or 0 for unknown. */ > +/* Return the width of the DRAM bus. */ > static int bus_width(void) > { > int full_width = 0; > @@ -228,17 +228,11 @@ static int bus_width(void) > if (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS)) > full_width = 1; > > - switch (mvebu_soc_family()) { > - case MVEBU_SOC_AXP: > - return full_width ? 64 : 32; > - break; > - case MVEBU_SOC_A375: > - case MVEBU_SOC_A38X: > - case MVEBU_SOC_MSYS: > - return full_width ? 32 : 16; > - default: > - return 0; > - } > +#ifdef CONFIG_ARMADA_XP > + return full_width ? 64 : 32; > +#else > + return full_width ? 32 : 16; > +#endif > } > > static int cycle_mode(void) > diff --git a/arch/arm/mach-mvebu/include/mach/cpu.h b/arch/arm/mach-mvebu/include/mach/cpu.h > index 9109f0c2582d..df0bb3c1bddd 100644 > --- a/arch/arm/mach-mvebu/include/mach/cpu.h > +++ b/arch/arm/mach-mvebu/include/mach/cpu.h > @@ -61,14 +61,6 @@ enum cpu_attrib { > CPU_ATTR_DEV_CS3 = 0x37, > }; > > -enum { > - MVEBU_SOC_AXP, > - MVEBU_SOC_A375, > - MVEBU_SOC_A38X, > - MVEBU_SOC_MSYS, > - MVEBU_SOC_UNKNOWN, > -}; > - > #define MVEBU_SDRAM_SIZE_MAX 0xc0000000 > > /* > @@ -151,7 +143,6 @@ unsigned int mvebu_sdram_bar(enum memory_bank bank); > unsigned int mvebu_sdram_bs(enum memory_bank bank); > void mvebu_sdram_size_adjust(enum memory_bank bank); > int mvebu_mbus_probe(struct mbus_win windows[], int count); > -int mvebu_soc_family(void); > u32 mvebu_get_nand_clock(void); > > void __noreturn return_to_bootrom(void); Viele Grüße, Stefan Roese -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de