[U-Boot] [powerpc NOR flash start address]

[U-Boot] [powerpc NOR flash start address]

[Yuri Frolov]

Hello,

probably an obvious question, but nevertheless...

More than a year ago, u-boot binary size was incfreased for powerpc boards (commit e222b1f36fedb0363dbc21e0add7dc3848bae553 "powerpc/mpc85xx:Increase binary size for P, B & T series boards."), so CONFIG_SYS_TEXT_BASE changed from 0xeff80000 to 0xeff40000.

I've been using Freescale P2041RDB-PA, rev. A board with U-Boot 2011.09-00000-g2c02d1d flashed to NOR at 0xeff80000 and running properly.

I'd like to update u-boot (rcw, fmac microcode, etc) hence, I need to flash u-boot binary at 0xeff40000.

The question is: which way does hardware know from which NOR flash address to begin to start?
After reset, powerpc cpus start to execute code from the 0xfffffffc address, which is usually (or, to say better - almost always) the last word of NOR flash); there is 0x4bfff004 at that address, which means "jump to 0xfffff000", if I understand it correctly. What code resides here and what does it do?

And, more practical question, where (and how) the hardware is given to understand, that it should look for u-boot image at particular NOR address?
What (and where) should I fix to change hardware's understanding of u-boot image location from  0xeff80000 to 0xeff40000?

TIA,
Yuri

[U-Boot] [powerpc NOR flash start address]

[Bin Meng]

Hi Yuri,

On Mon, Jul 20, 2015 at 9:54 PM, Yuri Frolov <yfrolov-uboot@yandex.ru> wrote:
> Hello,
>
> probably an obvious question, but nevertheless...
>
> More than a year ago, u-boot binary size was incfreased for powerpc boards (commit e222b1f36fedb0363dbc21e0add7dc3848bae553 "powerpc/mpc85xx:Increase binary size for P, B & T series boards."), so CONFIG_SYS_TEXT_BASE changed from 0xeff80000 to 0xeff40000.
>
> I've been using Freescale P2041RDB-PA, rev. A board with U-Boot 2011.09-00000-g2c02d1d flashed to NOR at 0xeff80000 and running properly.
>
> I'd like to update u-boot (rcw, fmac microcode, etc) hence, I need to flash u-boot binary at 0xeff40000.
>
> The question is: which way does hardware know from which NOR flash address to begin to start?
> After reset, powerpc cpus start to execute code from the 0xfffffffc address, which is usually (or, to say better - almost always) the last word of NOR flash); there is 0x4bfff004 at that address, which means "jump to 0xfffff000", if I understand it correctly. What code resides here and what does it do?

PowerPC BookE processors only map the last 4KiB page below 4GiB after
power-up. That's why you see the 'jump to 0xfffff000' at the 4GiB-4
address. As for 0xfffff000, it is arch/powerpc/cpu/mpc85xx/start.S
which is controlled by the linker script
arch/powerpc/cpu/mpc85xx/u-boot.lds.

>
> And, more practical question, where (and how) the hardware is given to understand, that it should look for u-boot image at particular NOR address?
> What (and where) should I fix to change hardware's understanding of u-boot image location from  0xeff80000 to 0xeff40000?
>

At power-up, hardware only knows 0xfffffffc which defaults decodes to
NOR flash if hardware configuration (either pins on old QUICC III, or
RCW on later QorIQ parts) points boot source to NOR. It is up to
bootloader (in this case U-Boot) to program the NOR flash address
later. This involves programming eLBC (for QUICC III) or IFC (for
QorIQ).

Regards,
Bin