From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3A815C48BE5 for ; Mon, 21 Jun 2021 09:02:37 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 7B2E161002 for ; Mon, 21 Jun 2021 09:02:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 7B2E161002 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=sntech.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 07D5382917; Mon, 21 Jun 2021 11:02:33 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sntech.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id E2A0582959; Mon, 21 Jun 2021 11:02:30 +0200 (CEST) Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id F395F801FD for ; Mon, 21 Jun 2021 11:02:27 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sntech.de Authentication-Results: phobos.denx.de; spf=none smtp.mailfrom=heiko@sntech.de Received: from ip5f5aa64a.dynamic.kabel-deutschland.de ([95.90.166.74] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1lvFp3-0008CY-99; Mon, 21 Jun 2021 11:02:25 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: kever.yang@rock-chips.com, Johan Jonker Cc: sjg@chromium.org, philipp.tomsich@vrull.eu, paweljarosz3691@gmail.com, u-boot@lists.denx.de Subject: Re: [PATCH v1] rockchip: rk3188-cru-common: sync clock dt-binding header from Linux Date: Mon, 21 Jun 2021 11:02:24 +0200 Message-ID: <3974273.bgRvk7e4E5@diego> In-Reply-To: <20210621073920.2675-1-jbx6244@gmail.com> References: <20210621073920.2675-1-jbx6244@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Am Montag, 21. Juni 2021, 09:39:20 CEST schrieb Johan Jonker: > In order to update the DT for rk3066 and rk3188 > sync the clock dt-binding header. > This is the state as of v5.12 in Linux. > > Signed-off-by: Johan Jonker Reviewed-by: Heiko Stuebner > --- > include/dt-bindings/clock/rk3188-cru-common.h | 12 +++++++++--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/include/dt-bindings/clock/rk3188-cru-common.h b/include/dt-bindings/clock/rk3188-cru-common.h > index 1e7931da0c..afad90680f 100644 > --- a/include/dt-bindings/clock/rk3188-cru-common.h > +++ b/include/dt-bindings/clock/rk3188-cru-common.h > @@ -1,4 +1,4 @@ > -/* SPDX-License-Identifier: GPL-2.0+ */ > +/* SPDX-License-Identifier: GPL-2.0-or-later */ > /* > * Copyright (c) 2014 MundoReader S.L. > * Author: Heiko Stuebner > @@ -59,12 +59,14 @@ > #define ACLK_LCDC1 196 > #define ACLK_GPU 197 > #define ACLK_SMC 198 > -#define ACLK_CIF 199 > +#define ACLK_CIF1 199 > #define ACLK_IPP 200 > #define ACLK_RGA 201 > #define ACLK_CIF0 202 > #define ACLK_CPU 203 > #define ACLK_PERI 204 > +#define ACLK_VEPU 205 > +#define ACLK_VDPU 206 > > /* pclk gates */ > #define PCLK_GRF 320 > @@ -125,8 +127,12 @@ > #define HCLK_NANDC0 467 > #define HCLK_CPU 468 > #define HCLK_PERI 469 > +#define HCLK_CIF1 470 > +#define HCLK_VEPU 471 > +#define HCLK_VDPU 472 > +#define HCLK_HDMI 473 > > -#define CLK_NR_CLKS (HCLK_PERI + 1) > +#define CLK_NR_CLKS (HCLK_HDMI + 1) > > /* soft-reset indices */ > #define SRST_MCORE 2 >