* [PATCH] clk: zynqmp: Add set_rate support for gem rx and tsu clks
@ 2023-07-19 8:49 Ashok Reddy Soma
2023-07-21 7:01 ` Michal Simek
0 siblings, 1 reply; 2+ messages in thread
From: Ashok Reddy Soma @ 2023-07-19 8:49 UTC (permalink / raw)
To: u-boot; +Cc: michal.simek, lukma, seanga2, git, Ashok Reddy Soma
gem0_rx till gem3_rx and gem_tsu are missing from set rate function.
Add them, so that they can be set from pmu firmware via clock framework.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
---
drivers/clk/clk_zynqmp.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index be0ee50e0e..27479391e1 100644
--- a/drivers/clk/clk_zynqmp.c
+++ b/drivers/clk/clk_zynqmp.c
@@ -718,6 +718,8 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
switch (id) {
case gem0_ref ... gem3_ref:
case gem0_tx ... gem3_tx:
+ case gem0_rx ... gem3_rx:
+ case gem_tsu:
case qspi_ref ... can1_ref:
case usb0_bus_ref ... usb3_dual_ref:
return zynqmp_clk_set_peripheral_rate(priv, id,
--
2.17.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] clk: zynqmp: Add set_rate support for gem rx and tsu clks
2023-07-19 8:49 [PATCH] clk: zynqmp: Add set_rate support for gem rx and tsu clks Ashok Reddy Soma
@ 2023-07-21 7:01 ` Michal Simek
0 siblings, 0 replies; 2+ messages in thread
From: Michal Simek @ 2023-07-21 7:01 UTC (permalink / raw)
To: Ashok Reddy Soma, u-boot; +Cc: lukma, seanga2, git
On 7/19/23 10:49, Ashok Reddy Soma wrote:
> gem0_rx till gem3_rx and gem_tsu are missing from set rate function.
> Add them, so that they can be set from pmu firmware via clock framework.
>
> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
> ---
>
> drivers/clk/clk_zynqmp.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
> index be0ee50e0e..27479391e1 100644
> --- a/drivers/clk/clk_zynqmp.c
> +++ b/drivers/clk/clk_zynqmp.c
> @@ -718,6 +718,8 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
> switch (id) {
> case gem0_ref ... gem3_ref:
> case gem0_tx ... gem3_tx:
> + case gem0_rx ... gem3_rx:
> + case gem_tsu:
> case qspi_ref ... can1_ref:
> case usb0_bus_ref ... usb3_dual_ref:
> return zynqmp_clk_set_peripheral_rate(priv, id,
Applied.
M
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2023-07-19 8:49 [PATCH] clk: zynqmp: Add set_rate support for gem rx and tsu clks Ashok Reddy Soma
2023-07-21 7:01 ` Michal Simek
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