From: Geir Thomassen <chaos@in.fer.no>
To: u-boot@lists.denx.de
Subject: [U-Boot-Users] [ANNOUNCE] u-boot-ptx-20030213-1
Date: Thu, 13 Feb 2003 10:28:23 +0100 [thread overview]
Message-ID: <3E4B6537.8020602@in.fer.no> (raw)
In-Reply-To: <20030213081716.GL10342@pengutronix.de>
From your patch (memsetup.S, various versions ..)
/* Step 4f: Trigger a number (usually 8) refresh cycles by */
/* attempting non-burst read or write accesses to disabled */
/* SDRAM, as commonly specified in the power up sequence */
/* documented in SDRAM data sheets. The address(es) used */
/* for this purpose must not be cacheable. */
ldr r3, =CFG_DRAM_BASE
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
str r2, [r3]
There should 9 writes, since the first write doesn't trigger a refresh
cycle on PXA250. See Intel? PXA250 and PXA210 Processors Specification
Update, Jan 2003, Errata #116, page 30.
.rept 9
str r2, [r2]
.endr
--
Geir
next prev parent reply other threads:[~2003-02-13 9:28 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-02-13 8:17 [U-Boot-Users] [ANNOUNCE] u-boot-ptx-20030213-1 Robert Schwebel
2003-02-13 9:20 ` Geir Thomassen
2003-02-13 9:48 ` Robert Schwebel
2003-02-13 12:23 ` Wolfgang Denk
2003-02-13 9:28 ` Geir Thomassen [this message]
2003-02-13 9:53 ` Robert Schwebel
2003-02-13 20:42 ` Geir Thomassen
2003-02-13 21:28 ` Robert Schwebel
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