From mboxrd@z Thu Jan 1 00:00:00 1970 From: Geir Thomassen Date: Thu, 13 Feb 2003 10:28:23 +0100 Subject: [U-Boot-Users] [ANNOUNCE] u-boot-ptx-20030213-1 In-Reply-To: <20030213081716.GL10342@pengutronix.de> References: <20030213081716.GL10342@pengutronix.de> Message-ID: <3E4B6537.8020602@in.fer.no> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de From your patch (memsetup.S, various versions ..) /* Step 4f: Trigger a number (usually 8) refresh cycles by */ /* attempting non-burst read or write accesses to disabled */ /* SDRAM, as commonly specified in the power up sequence */ /* documented in SDRAM data sheets. The address(es) used */ /* for this purpose must not be cacheable. */ ldr r3, =CFG_DRAM_BASE str r2, [r3] str r2, [r3] str r2, [r3] str r2, [r3] str r2, [r3] str r2, [r3] str r2, [r3] str r2, [r3] There should 9 writes, since the first write doesn't trigger a refresh cycle on PXA250. See Intel? PXA250 and PXA210 Processors Specification Update, Jan 2003, Errata #116, page 30. .rept 9 str r2, [r2] .endr -- Geir