From mboxrd@z Thu Jan 1 00:00:00 1970 From: Steven Scholz Date: Tue, 21 Oct 2003 15:54:49 +0200 Subject: [U-Boot-Users] How to optimize bit bang interface? Message-ID: <3F953AA9.5070300@imc-berlin.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi there, I am trying to configure an Altera FPGA using the so called "passive serial interface". Basicly it follows the scheme "clk low, data out, clock high". For testing I wrote the loop ts = get_timer (0); while (1) { if (get_timer (ts) > 10 * CFG_HZ) break; /* Deassert the clock */ (*fn->clk) (FALSE, TRUE, cookie); /* Assert the clock */ (*fn->clk) (TRUE, TRUE, cookie); }; fn->clk() is the function that the common FPGA code uses: int inline fpga_clk_fn(int assert_clk, int flush, int cookie) { if (assert_clk) *AT91C_PIOB_SODR = FPGA_DCLK; else *AT91C_PIOB_CODR = FPGA_DCLK; return assert_clk; } I noticed that this is awfully slow. I get arounf 50kHz using an AT91RM9200 running at 51MHz (core @ 171MHz). Could someone give me a hint how to optimize stuff like this for speed? Thanks a million, -- Steven Scholz imc Measurement & Control imc Me?systeme GmbH Voltastr. 5 Voltastr. 5 13355 Berlin 13355 Berlin Germany Deutschland fon: +49 30 467090-0 Tel: 030 / 467090-0 fax: +49 30 4631576 fax: 030 / 4631576