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Thu, 24 Feb 2022 09:03:52 +0900 (KST) Received: from [10.113.113.235] (unknown [10.113.113.235]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20220224000352epsmtip2e7895cca3a103d3c3f986693c0470c46~Wj-10S9p62628226282epsmtip2Q; Thu, 24 Feb 2022 00:03:52 +0000 (GMT) Message-ID: <3adccccb-85b0-2b20-860c-5108bbd84edb@samsung.com> Date: Thu, 24 Feb 2022 09:03:52 +0900 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Subject: Re: [PATCH v2] mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON when necessary Content-Language: en-US To: haibo.chen@nxp.com, peng.fan@nxp.com, festevam@gmail.com, sean.anderson@seco.com, u-boot@lists.denx.de, marex@denx.de, aford173@gmail.com, tharvey@gateworks.com, andrey.zhizhikin@leica-geosystems.com Cc: uboot-imx@nxp.com From: Jaehoon Chung In-Reply-To: <1645500498-5500-1-git-send-email-haibo.chen@nxp.com> Content-Transfer-Encoding: 8bit X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrIJsWRmVeSWpSXmKPExsWy7bCmnm7mabEkg+unpS3u3D7NbPHs+TtW i4dX/S36r65ktHjT1sho8WPVF1aLefdbmCwunvjEbPF2bye7xZTH69kduDzmzTrB4nGu5y6b x85Zd9k9Hh56weZx9s4ORo+N73YweTz79409gD0q2yYjNTEltUghNS85PyUzL91WyTs43jne 1MzAUNfQ0sJcSSEvMTfVVsnFJ0DXLTMH6D4lhbLEnFKgUEBicbGSvp1NUX5pSapCRn5xia1S akFKToFpgV5xYm5xaV66Xl5qiZWhgYGRKVBhQnbGlZvH2Av+alV8WmHRwPhUqYuRk0NCwETi 6c0DjF2MXBxCAjsYJfYvOssM4XxilFjy9ykrhPONUWJ1/1o2mJbn02eyQyT2MkpMWfSaESQh JPCeUeL3Jy8Qm1fATuLguRVgDSwCqhLzL65ngYgLSpyc+QTMFhWIkHh55C8TiC0MZM/dOB1s DrOAuMStJ/OZQBaICFxklDh64x+QwwGUEJW4eJ8LpIZNQEdi+7fjYL2cAk4SU5YeZYPolZdo 3job7AUJgR0cEv1nepggrnaR2LPkKiOELSzx6vgWdghbSuLzu71sEA3NjBJLlxxkhXB6GCX+ NVyH+tlYYv/SyVBXaEqs36UPEVaU2Pl7LtTVfBLvvvawgpRICPBKdLQJQZSoSFx6/ZIJZtfd J/9ZIWwPiQ8dN9gnMCrOQgqXWUj+n4Xkn1kIixcwsqxiFEstKM5NTy02LDCGx3Zyfu4mRnDa 1TLfwTjt7Qe9Q4xMHIyHGCU4mJVEeE0LxZKEeFMSK6tSi/Lji0pzUosPMZoCY2cis5Rocj4w 8eeVxBuaWBqYmBkZm1gYmhkqifOumnY6UUggPbEkNTs1tSC1CKaPiYNTqoHJWtHn79MvWa8l /to/+HlAssJ4YuRBx0eqfr9EPdpfKbyd8UPf3aGj7EL8tvXn9VauU+pjfvRyxRYzn+/u6kd5 vNz9j23rk9mV679Yb9602lOKH0+sf3aW6bZl7KnAl2Z7toX5szWkL5rBVjN37ZJtThy65Uo2 J/bLqiyr2fqxZrvEXS/RCP/+1tovEWLdD07HP+aOuvogurbpUKnYhaBtfdErk+xVV9+9cvvv 57PCv+KK5DRLtvkvORI7/cinw/lF3/5wnPf0tpRqbZ1yUnTNwUkCcqfOh5ZHFO24ZyiYuviS QPDD9iSJKZueOTOtWKqXeLHDmL/agNHBoWJrrNRW/6aC2S3RlpGMaTOvSV9WYinOSDTUYi4q TgQAovFfqkQEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphkeLIzCtJLcpLzFFi42LZdlhJXjfjtFiSwbv71hZ3bp9mtnj2/B2r xcOr/hb9V1cyWrxpa2S0+LHqC6vFvPstTBYXT3xitni7t5PdYsrj9ewOXB7zZp1g8TjXc5fN Y+esu+weDw+9YPM4e2cHo8fGdzuYPJ79+8YewB7FZZOSmpNZllqkb5fAlXHl5jH2gr9aFZ9W WDQwPlXqYuTkkBAwkXg+fSZ7FyMXh5DAbkaJC1cWsEMkpCQ+P53K1sXIAWQLSxw+XAxR85ZR 4sX3j6wgNbwCdhIHz61gA7FZBFQl5l9czwIRF5Q4OfMJmC0qECHRtmwKM4gtDGTP3TidEcRm FhCXuPVkPhPIUBGBi4wSk650MoIsYxYQlbh4nwukRkhgKqPE9DMOIDabgI7E9m/HmUBsTgEn iSlLj7JBlKtLrJ8nBDFSXqJ562zmCYxCs5BcMQvJtlkIHbOQdCxgZFnFKJlaUJybnltsWGCY l1quV5yYW1yal66XnJ+7iREcYVqaOxi3r/qgd4iRiYPxEKMEB7OSCK9poViSEG9KYmVValF+ fFFpTmrxIUZpDhYlcd4LXSfjhQTSE0tSs1NTC1KLYLJMHJxSDUztYVMf7NrlvKvVmeOVcZ7G nOctzG32xe42OScnT59y84e3ubbUmeX6F3Z73X00y4LTuUjEl23JVd/Fyganjm++6bXVUJfh T8PkxRuc79SHakv6Ky/Tv3VKcsfR+yfm2ufMSpC2kxadqM5SsePvd2PzzKn3H1ff/C1dY+G9 fu8Wg9XnbvOsurvnveCSFdwL024JGuxPYQ/8kLhJ+n7z9dSQCY3lx/i//dc+tnDLo/VJQr0/ W1g1V0TrXMub4P9fN+Rwn3Xl3wmiB0tOPb/09Ld//MO1cwteOLMfvV26ZvHULduuLdt1yFBv +mGjGZJLpucmml2buk363PMd636WznNiirLRWrRlppiZzb1AptgwdiWW4oxEQy3mouJEAO+O 6ugfAwAA X-CMS-MailID: 20220224000353epcas1p4123afca960b50c83926af27b5d4e871a X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: SVC_REQ_APPROVE CMS-TYPE: 101P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220222033658epcas1p4d233f0d3c4a5c59f50609c7589c72379 References: <1645500498-5500-1-git-send-email-haibo.chen@nxp.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On 2/22/22 12:28, haibo.chen@nxp.com wrote: > From: Haibo Chen > > After commit f132aab40327 ("Revert "mmc: fsl_esdhc_imx: use > VENDORSPEC_FRC_SDCLK_ON to control card clock output""), it > involve issue in mmc_switch_voltage(), because of the special > design of usdhc. > > For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, > these are reserved bits(Though RM contain the definition of these bits, > but actually internal IC logic do not implement, already confirm with > IC team). Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card > clock output. Here is the definition of this bit in RM: > > [8] FRC_SDCLK_ON > Force CLK output active > Do not set this bit to 1 unless it is necessary. Also, make sure that > this bit is cleared when uSDHC’s clock is about to be changed (frequency > change, clock source change, or delay chain tuning). > 0b - CLK active or inactive is fully controlled by the hardware. > 1b - Force CLK active > > In default, the FRC_SDCLK_ON is 0. This means, when there is no command > or data transfer on bus, hardware will gate off the card clock. But in > some case, we need the card clock keep on. Take IO voltage 1.8v switch > as example, after IO voltage change to 1.8v, spec require gate off the > card clock for 5ms, and gate on the clock back, once detect the card > clock on, then the card will draw the dat0 to high immediately. If there > is not clock gate off/on behavior, some card will keep the dat0 to low > level. This is the reason we fail in mmc_switch_voltage(). > > To fix this issue, and concern that this is only the fsl usdhc hardware > design limitation, set the bit FRC_SDCLK_ON in the beginning of the > wait_dat0() and clear it in the end. To make sure the 1.8v IO voltage > switch process align with SD specification. > > For standard tuning process, usdhc specification also require the card > clock keep on, so also add these behavior in fsl_esdhc_execute_tuning(). > > Reviewed-by: Marek Vasut > Tested-by: Fabio Estevam > Signed-off-by: Haibo Chen Reviewed-by: Jaehoon Chung Best Regards, Jaehoon Chung > --- > drivers/mmc/fsl_esdhc_imx.c | 25 ++++++++++++++++++++++--- > include/fsl_esdhc_imx.h | 2 ++ > 2 files changed, 24 insertions(+), 3 deletions(-) > > diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c > index 9299635f50..e0108144e7 100644 > --- a/drivers/mmc/fsl_esdhc_imx.c > +++ b/drivers/mmc/fsl_esdhc_imx.c > @@ -831,13 +831,16 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) > struct mmc *mmc = &plat->mmc; > u32 irqstaten = esdhc_read32(®s->irqstaten); > u32 irqsigen = esdhc_read32(®s->irqsigen); > - int i, ret = -ETIMEDOUT; > - u32 val, mixctrl; > + int i, err, ret = -ETIMEDOUT; > + u32 val, mixctrl, tmp; > > /* clock tuning is not needed for upto 52MHz */ > if (mmc->clock <= 52000000) > return 0; > > + /* make sure the card clock keep on */ > + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); > + > /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */ > if (priv->flags & ESDHC_FLAG_STD_TUNING) { > val = esdhc_read32(®s->autoc12err); > @@ -897,6 +900,12 @@ static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode) > > esdhc_stop_tuning(mmc); > > + /* change to default setting, let host control the card clock */ > + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); > + err = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); > + if (err) > + dev_warn(dev, "card clock not gate off as expect.\n"); > + > return ret; > } > #endif > @@ -1555,14 +1564,24 @@ static int __maybe_unused fsl_esdhc_set_enhanced_strobe(struct udevice *dev) > static int fsl_esdhc_wait_dat0(struct udevice *dev, int state, > int timeout_us) > { > - int ret; > + int ret, err; > u32 tmp; > struct fsl_esdhc_priv *priv = dev_get_priv(dev); > struct fsl_esdhc *regs = priv->esdhc_regs; > > + /* make sure the card clock keep on */ > + esdhc_setbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); > + > ret = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, > !!(tmp & PRSSTAT_DAT0) == !!state, > timeout_us); > + > + /* change to default setting, let host control the card clock */ > + esdhc_clrbits32(®s->vendorspec, VENDORSPEC_FRC_SDCLK_ON); > + err = readx_poll_timeout(esdhc_read32, ®s->prsstat, tmp, tmp & PRSSTAT_SDOFF, 100); > + if (err) > + dev_warn(dev, "card clock not gate off as expect.\n"); > + > return ret; > } > > diff --git a/include/fsl_esdhc_imx.h b/include/fsl_esdhc_imx.h > index 2153f29bef..b8efd2a166 100644 > --- a/include/fsl_esdhc_imx.h > +++ b/include/fsl_esdhc_imx.h > @@ -37,6 +37,7 @@ > #define VENDORSPEC_HCKEN 0x00001000 > #define VENDORSPEC_IPGEN 0x00000800 > #define VENDORSPEC_INIT 0x20007809 > +#define VENDORSPEC_FRC_SDCLK_ON 0x00000100 > > #define IRQSTAT 0x0002e030 > #define IRQSTAT_DMAE (0x10000000) > @@ -94,6 +95,7 @@ > #define PRSSTAT_CINS (0x00010000) > #define PRSSTAT_BREN (0x00000800) > #define PRSSTAT_BWEN (0x00000400) > +#define PRSSTAT_SDOFF (0x00000080) > #define PRSSTAT_SDSTB (0X00000008) > #define PRSSTAT_DLA (0x00000004) > #define PRSSTAT_CICHB (0x00000002)