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Tue, 26 Apr 2022 14:17:53 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 62D8210002A; Tue, 26 Apr 2022 14:17:53 +0200 (CEST) Received: from Webmail-eu.st.com (sfhdag2node2.st.com [10.75.127.5]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 551B9222CA9; Tue, 26 Apr 2022 14:17:53 +0200 (CEST) Received: from [10.48.0.213] (10.75.127.47) by SFHDAG2NODE2.st.com (10.75.127.5) with Microsoft SMTP Server (TLS) id 15.0.1497.26; Tue, 26 Apr 2022 14:17:52 +0200 Message-ID: <3b978d3f-e33f-dfdf-76a7-3fdde0bbd005@foss.st.com> Date: Tue, 26 Apr 2022 14:17:52 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [PATCH] stm32mp: psci: Retain PLL3CR, PLL4CR, RCC_MSSCKSELR across suspend Content-Language: en-US To: Marek Vasut , CC: Patrice Chotard References: <20220414021635.504165-1-marex@denx.de> From: Patrick DELAUNAY In-Reply-To: <20220414021635.504165-1-marex@denx.de> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-04-26_02,2022-04-26_01,2022-02-23_01 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean Hi, On 4/14/22 04:16, Marek Vasut wrote: > The SoC seems to lose the values of PLL3CR, PLL4CR, RCC_MSSCKSELR > during suspend/resume cycle, cache them and reinstate their values > on resume. > > Signed-off-by: Marek Vasut > Cc: Patrick Delaunay > Cc: Patrice Chotard > --- > arch/arm/mach-stm32mp/psci.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c > index 86c160987a9..b2988b3d993 100644 > --- a/arch/arm/mach-stm32mp/psci.c > +++ b/arch/arm/mach-stm32mp/psci.c > @@ -26,6 +26,7 @@ > #define PWR_MPUCR_CSSF BIT(9) > > /* RCC */ > +#define RCC_MSSCKSELR 0x48 > #define RCC_DDRITFCR 0xd8 > > #define RCC_DDRITFCR_DDRC1EN BIT(0) > @@ -49,6 +50,9 @@ > #define RCC_MP_CIFR 0x418 > #define RCC_MP_CIFR_WKUPF BIT(20) > > +#define RCC_PLL3CR 0x880 > +#define RCC_PLL4CR 0x894 > + > /* SYSCFG */ > #define SYSCFG_CMPCR 0x20 > #define SYSCFG_CMPCR_SW_CTRL BIT(2) > @@ -690,6 +694,7 @@ static void __secure ddr_sw_self_refresh_exit(void) > void __secure psci_system_suspend(u32 __always_unused function_id, > u32 ep, u32 context_id) > { > + u32 saved_pll3cr, saved_pll4cr, saved_mssckselr; > u32 saved_pwrctl, reg; > > /* Disable IO compensation */ > @@ -708,6 +713,10 @@ void __secure psci_system_suspend(u32 __always_unused function_id, > setbits_le32(STM32_PWR_BASE + PWR_MPUCR, > PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS); > > + saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR); > + saved_pll4cr = readl(STM32_RCC_BASE + RCC_PLL4CR); > + saved_mssckselr = readl(STM32_RCC_BASE + RCC_MSSCKSELR); > + > psci_v7_flush_dcache_all(); > ddr_sr_mode_ssr(&saved_pwrctl); > ddr_sw_self_refresh_in(); > @@ -724,6 +733,10 @@ void __secure psci_system_suspend(u32 __always_unused function_id, > ddr_sw_self_refresh_exit(); > ddr_sr_mode_restore(saved_pwrctl); > > + writel(saved_pll3cr, STM32_RCC_BASE + RCC_PLL3CR); > + writel(saved_pll4cr, STM32_RCC_BASE + RCC_PLL4CR); > + writel(saved_mssckselr, STM32_RCC_BASE + RCC_MSSCKSELR); need to save and restore RCC_MCUDIVR also I think. based on TF-A drivers/st/clk/stm32mp1_clk.c::stm32mp1_clock_stopmode_resume() > + > writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR); > clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL); > } Patrick