* [PATCH] stm32mp: psci: Retain PLL3CR, PLL4CR, RCC_MSSCKSELR across suspend
@ 2022-04-14 2:16 Marek Vasut
2022-04-22 8:37 ` Patrice CHOTARD
2022-04-26 12:17 ` Patrick DELAUNAY
0 siblings, 2 replies; 3+ messages in thread
From: Marek Vasut @ 2022-04-14 2:16 UTC (permalink / raw)
To: u-boot; +Cc: Marek Vasut, Patrick Delaunay, Patrice Chotard
The SoC seems to lose the values of PLL3CR, PLL4CR, RCC_MSSCKSELR
during suspend/resume cycle, cache them and reinstate their values
on resume.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
Cc: Patrice Chotard <patrice.chotard@foss.st.com>
---
arch/arm/mach-stm32mp/psci.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c
index 86c160987a9..b2988b3d993 100644
--- a/arch/arm/mach-stm32mp/psci.c
+++ b/arch/arm/mach-stm32mp/psci.c
@@ -26,6 +26,7 @@
#define PWR_MPUCR_CSSF BIT(9)
/* RCC */
+#define RCC_MSSCKSELR 0x48
#define RCC_DDRITFCR 0xd8
#define RCC_DDRITFCR_DDRC1EN BIT(0)
@@ -49,6 +50,9 @@
#define RCC_MP_CIFR 0x418
#define RCC_MP_CIFR_WKUPF BIT(20)
+#define RCC_PLL3CR 0x880
+#define RCC_PLL4CR 0x894
+
/* SYSCFG */
#define SYSCFG_CMPCR 0x20
#define SYSCFG_CMPCR_SW_CTRL BIT(2)
@@ -690,6 +694,7 @@ static void __secure ddr_sw_self_refresh_exit(void)
void __secure psci_system_suspend(u32 __always_unused function_id,
u32 ep, u32 context_id)
{
+ u32 saved_pll3cr, saved_pll4cr, saved_mssckselr;
u32 saved_pwrctl, reg;
/* Disable IO compensation */
@@ -708,6 +713,10 @@ void __secure psci_system_suspend(u32 __always_unused function_id,
setbits_le32(STM32_PWR_BASE + PWR_MPUCR,
PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS);
+ saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR);
+ saved_pll4cr = readl(STM32_RCC_BASE + RCC_PLL4CR);
+ saved_mssckselr = readl(STM32_RCC_BASE + RCC_MSSCKSELR);
+
psci_v7_flush_dcache_all();
ddr_sr_mode_ssr(&saved_pwrctl);
ddr_sw_self_refresh_in();
@@ -724,6 +733,10 @@ void __secure psci_system_suspend(u32 __always_unused function_id,
ddr_sw_self_refresh_exit();
ddr_sr_mode_restore(saved_pwrctl);
+ writel(saved_pll3cr, STM32_RCC_BASE + RCC_PLL3CR);
+ writel(saved_pll4cr, STM32_RCC_BASE + RCC_PLL4CR);
+ writel(saved_mssckselr, STM32_RCC_BASE + RCC_MSSCKSELR);
+
writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
}
--
2.35.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] stm32mp: psci: Retain PLL3CR, PLL4CR, RCC_MSSCKSELR across suspend
2022-04-14 2:16 [PATCH] stm32mp: psci: Retain PLL3CR, PLL4CR, RCC_MSSCKSELR across suspend Marek Vasut
@ 2022-04-22 8:37 ` Patrice CHOTARD
2022-04-26 12:17 ` Patrick DELAUNAY
1 sibling, 0 replies; 3+ messages in thread
From: Patrice CHOTARD @ 2022-04-22 8:37 UTC (permalink / raw)
To: Marek Vasut, u-boot; +Cc: Patrick Delaunay
HI Marek
On 4/14/22 04:16, Marek Vasut wrote:
> The SoC seems to lose the values of PLL3CR, PLL4CR, RCC_MSSCKSELR
> during suspend/resume cycle, cache them and reinstate their values
> on resume.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
> Cc: Patrice Chotard <patrice.chotard@foss.st.com>
> ---
> arch/arm/mach-stm32mp/psci.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c
> index 86c160987a9..b2988b3d993 100644
> --- a/arch/arm/mach-stm32mp/psci.c
> +++ b/arch/arm/mach-stm32mp/psci.c
> @@ -26,6 +26,7 @@
> #define PWR_MPUCR_CSSF BIT(9)
>
> /* RCC */
> +#define RCC_MSSCKSELR 0x48
> #define RCC_DDRITFCR 0xd8
>
> #define RCC_DDRITFCR_DDRC1EN BIT(0)
> @@ -49,6 +50,9 @@
> #define RCC_MP_CIFR 0x418
> #define RCC_MP_CIFR_WKUPF BIT(20)
>
> +#define RCC_PLL3CR 0x880
> +#define RCC_PLL4CR 0x894
> +
> /* SYSCFG */
> #define SYSCFG_CMPCR 0x20
> #define SYSCFG_CMPCR_SW_CTRL BIT(2)
> @@ -690,6 +694,7 @@ static void __secure ddr_sw_self_refresh_exit(void)
> void __secure psci_system_suspend(u32 __always_unused function_id,
> u32 ep, u32 context_id)
> {
> + u32 saved_pll3cr, saved_pll4cr, saved_mssckselr;
> u32 saved_pwrctl, reg;
>
> /* Disable IO compensation */
> @@ -708,6 +713,10 @@ void __secure psci_system_suspend(u32 __always_unused function_id,
> setbits_le32(STM32_PWR_BASE + PWR_MPUCR,
> PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS);
>
> + saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR);
> + saved_pll4cr = readl(STM32_RCC_BASE + RCC_PLL4CR);
> + saved_mssckselr = readl(STM32_RCC_BASE + RCC_MSSCKSELR);
> +
> psci_v7_flush_dcache_all();
> ddr_sr_mode_ssr(&saved_pwrctl);
> ddr_sw_self_refresh_in();
> @@ -724,6 +733,10 @@ void __secure psci_system_suspend(u32 __always_unused function_id,
> ddr_sw_self_refresh_exit();
> ddr_sr_mode_restore(saved_pwrctl);
>
> + writel(saved_pll3cr, STM32_RCC_BASE + RCC_PLL3CR);
> + writel(saved_pll4cr, STM32_RCC_BASE + RCC_PLL4CR);
> + writel(saved_mssckselr, STM32_RCC_BASE + RCC_MSSCKSELR);
> +
> writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
> clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
> }
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Thanks
Patrice
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] stm32mp: psci: Retain PLL3CR, PLL4CR, RCC_MSSCKSELR across suspend
2022-04-14 2:16 [PATCH] stm32mp: psci: Retain PLL3CR, PLL4CR, RCC_MSSCKSELR across suspend Marek Vasut
2022-04-22 8:37 ` Patrice CHOTARD
@ 2022-04-26 12:17 ` Patrick DELAUNAY
1 sibling, 0 replies; 3+ messages in thread
From: Patrick DELAUNAY @ 2022-04-26 12:17 UTC (permalink / raw)
To: Marek Vasut, u-boot; +Cc: Patrice Chotard
Hi,
On 4/14/22 04:16, Marek Vasut wrote:
> The SoC seems to lose the values of PLL3CR, PLL4CR, RCC_MSSCKSELR
> during suspend/resume cycle, cache them and reinstate their values
> on resume.
>
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Patrick Delaunay <patrick.delaunay@foss.st.com>
> Cc: Patrice Chotard <patrice.chotard@foss.st.com>
> ---
> arch/arm/mach-stm32mp/psci.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/psci.c
> index 86c160987a9..b2988b3d993 100644
> --- a/arch/arm/mach-stm32mp/psci.c
> +++ b/arch/arm/mach-stm32mp/psci.c
> @@ -26,6 +26,7 @@
> #define PWR_MPUCR_CSSF BIT(9)
>
> /* RCC */
> +#define RCC_MSSCKSELR 0x48
> #define RCC_DDRITFCR 0xd8
>
> #define RCC_DDRITFCR_DDRC1EN BIT(0)
> @@ -49,6 +50,9 @@
> #define RCC_MP_CIFR 0x418
> #define RCC_MP_CIFR_WKUPF BIT(20)
>
> +#define RCC_PLL3CR 0x880
> +#define RCC_PLL4CR 0x894
> +
> /* SYSCFG */
> #define SYSCFG_CMPCR 0x20
> #define SYSCFG_CMPCR_SW_CTRL BIT(2)
> @@ -690,6 +694,7 @@ static void __secure ddr_sw_self_refresh_exit(void)
> void __secure psci_system_suspend(u32 __always_unused function_id,
> u32 ep, u32 context_id)
> {
> + u32 saved_pll3cr, saved_pll4cr, saved_mssckselr;
> u32 saved_pwrctl, reg;
>
> /* Disable IO compensation */
> @@ -708,6 +713,10 @@ void __secure psci_system_suspend(u32 __always_unused function_id,
> setbits_le32(STM32_PWR_BASE + PWR_MPUCR,
> PWR_MPUCR_CSSF | PWR_MPUCR_CSTDBYDIS | PWR_MPUCR_PDDS);
>
> + saved_pll3cr = readl(STM32_RCC_BASE + RCC_PLL3CR);
> + saved_pll4cr = readl(STM32_RCC_BASE + RCC_PLL4CR);
> + saved_mssckselr = readl(STM32_RCC_BASE + RCC_MSSCKSELR);
> +
> psci_v7_flush_dcache_all();
> ddr_sr_mode_ssr(&saved_pwrctl);
> ddr_sw_self_refresh_in();
> @@ -724,6 +733,10 @@ void __secure psci_system_suspend(u32 __always_unused function_id,
> ddr_sw_self_refresh_exit();
> ddr_sr_mode_restore(saved_pwrctl);
>
> + writel(saved_pll3cr, STM32_RCC_BASE + RCC_PLL3CR);
> + writel(saved_pll4cr, STM32_RCC_BASE + RCC_PLL4CR);
> + writel(saved_mssckselr, STM32_RCC_BASE + RCC_MSSCKSELR);
need to save and restore RCC_MCUDIVR also I think.
based on TF-A
drivers/st/clk/stm32mp1_clk.c::stm32mp1_clock_stopmode_resume()
> +
> writel(SYSCFG_CMPENR_MPUEN, STM32_SYSCFG_BASE + SYSCFG_CMPENSETR);
> clrbits_le32(STM32_SYSCFG_BASE + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
> }
Patrick
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-04-14 2:16 [PATCH] stm32mp: psci: Retain PLL3CR, PLL4CR, RCC_MSSCKSELR across suspend Marek Vasut
2022-04-22 8:37 ` Patrice CHOTARD
2022-04-26 12:17 ` Patrick DELAUNAY
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