[U-Boot-Users] waiting for timeouts in FPGA code?

[Steven Scholz <steven.scholz@imc-berlin.de>]

Wolfgang Denk wrote:

> In message <403B84DB.40900@imc-berlin.de> you wrote:
> 
>>in the U-Boot FPGA code timeouts are realized by
>>
>>if (get_timer (ts) > CFG_FPGA_WAIT{_INIT})
>>	...
>>
>>while CFG_FPGA_WAIT{_INIT} is supposed to be the timeout in milliseconds.
> 
> Then this design is broken; get_timer() returns the number  of  timer
> ticks  (= CFG_HZ per second). This is only milliseconds for CFG_HZ ==
> 1000.

So I does not matter how fast the timer ticks as long as CFG_HZ is set 
to the correct value and timeouts are based on CFG_HZ. Correct?

>>This does not work for the AT91RM9200. Instead of using
>>
>>#define CFG_FPGA_WAIT 10
>>
>>I have to use
>>
>>#define CFG_FPGA_WAIT CFG_HZ/10
> 
> Note that this is ten times as long as the original timeout.
Of course. Typo.

>>Is CFG_HZ defined for all other architectures?
> It is supposed to be defined. But many boards define it incorrectly.
>>Should we use CFG_HZ instead of hardcoded numbers?
> Definitely.

Hmm. But that means that when we change e.g. the above mentioned FPGA 
code to use CFG_HZ that we might break these archictectures !?
-- 
Steven Scholz

imc Measurement & Control               imc Me?systeme GmbH
Voltastr. 5                             Voltastr. 5
13355 Berlin                            13355 Berlin
Germany                                 Deutschland