From mboxrd@z Thu Jan 1 00:00:00 1970 From: Steven Scholz Date: Wed, 25 Feb 2004 13:49:55 +0100 Subject: [U-Boot-Users] waiting for timeouts in FPGA code? In-Reply-To: <20040224222555.D7A8BC0655@atlas.denx.de> References: <20040224222555.D7A8BC0655@atlas.denx.de> Message-ID: <403C99F3.309@imc-berlin.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Wolfgang Denk wrote: >>Is CFG_HZ defined for all other architectures? > It is supposed to be defined. But many boards define it incorrectly. >>Should we use CFG_HZ instead of hardcoded numbers? > Definitely. Here we go: * Patch by Steven Scholz, 25 Feb 2004: - Timeouts in FPGA code should be based on CFG_HZ - Minor cleanup in code for Altera FPGA ACEX1K BTW: I just noticed that loads of timeouts (e.g. CFG_FLASH_ERASE_TOUT) are _not_ defined using CFG_HZ ... -- Steven Scholz imc Measurement & Control imc Me?systeme GmbH Voltastr. 5 Voltastr. 5 13355 Berlin 13355 Berlin Germany Deutschland -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: fpga-CFG_HZ.patch Url: http://lists.denx.de/pipermail/u-boot/attachments/20040225/f24e0a1b/attachment.txt