From mboxrd@z Thu Jan  1 00:00:00 1970
From: nafiton <jose.ferreiro@horushardware.com>
Date: Wed, 07 Apr 2004 18:12:15 +0200
Subject: [U-Boot-Users] IMMAP M5282  correct?
In-Reply-To: <40740F99.7090008@horus.es>
References: <40740F99.7090008@horus.es>
Message-ID: <4074285F.9070900@horushardware.com>
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To: u-boot@lists.denx.de

> I am having problems trying to use the net features on a new board 
> configuration.
> Is it possible that the include/asm-m68k/immap_5282.h file is wrong? 
> It seems to not coincide with Motorola documentation about its FEC 
> registers.
>
Well. I don?t know if this is the way to do it. Being a newbie, I must 
be missing something because as I see it, it is imposible that it worked 
before.

After I rebuild the immap file, the board started transmision but not 
received nothing. It was necessary to write the packet length on the FEC 
Receive Control Register ( just as it was necesary to do to make dBUG 
work - my first step with this new board :-) After it, the TFTP works 
very fine (curiosly, far finer then dBUG tftp :-)

Can you see what I am doing awrong?

Thank you

PD: This is the immap_5282.file that get the thing to work:

/* Fast ethernet controller registers
 */
typedef struct fec {
    uint    res1;                /* reserved                1000*/
    uint    fec_ievent;        /* interrupt event register        1004*/
    uint    fec_imask;        /* interrupt mask register        1008*/
    uint    res2;                /* reserved                100c*/
    uint    fec_r_des_active;    /* Rx ring updated flag            1010*/
    uint    fec_x_des_active;    /* Tx ring updated flag            1014*/
    uint    res3[3];        /* reserved                1018*/
    uint    fec_ecntrl;        /* ethernet control register        1024*/
    uint    res4[6];        /* reserved                1028*/
    uint    fec_mii_data;        /* MII data register            1040*/
    uint    fec_mii_speed;        /* MII speed control register        
1044*/
    uint    res5[7];        /* reserved                1048*/
    uint    fec_mibc;        /* MIB Control/Status register         1064*/
    uint    res6[7];        /* reserved                1068*/
    uint    fec_r_cntrl;        /* Rx control register            1084*/
    uint    res7[15];        /* reserved                1088*/
    uint    fec_x_cntrl;        /* Tx control register            10C4*/
    uint    res8[7];        /* reserved                10C8*/
    uint    fec_addr_low;        /* lower 32 bits of station address    
10E4*/
    uint    fec_addr_high;        /* upper 16 bits of station address + 
type field    10E8*/
    uint    fec_opd;        /* opcode + pause duration          10EC*/
    uint    res9[10];        /* reserved                10F0*/
    uint    fec_ihash_table_high;    /* upper 32-bits of individual hash 
table        1118*/
    uint    fec_ihash_table_low;    /* lower 32-bits of individual hash 
table        111C*/
    uint    fec_ghash_table_high;    /* upper 32-bits of group hash 
table    1120*/
    uint    fec_ghash_table_low;    /* lower 32-bits of group hash 
table    1124*/
    uint    res10[7];        /* reserved                1128*/
    uint    fec_tfwr;        /* Transmit FIFO watermark            1144*/
    uint    res11;            /* reserved                1148*/
    uint    fec_r_bound;        /* FIFO Receive Bound Register = end of 
RAM (read-only)    ???    114C*/
    uint    fec_r_fstart;        /* FIFO Receive FIfo Start Registers = 
Rx FIFO start address ??? 1150*/
    uint    res12[11];        /* reserved                1154*/
    uint    fec_r_des_start;    /* beginning of Rx descriptor ring    1180*/
    uint    fec_x_des_start;    /* beginning of Tx descriptor ring    1184*/
    uint    fec_r_buff_size;    /* Rx buffer size            118C*/
} fec_t;

>