* [U-Boot-Users] ppc440gx
@ 2004-09-02 17:10 Barbier, Renaud
2004-09-03 13:25 ` Ralph Siemsen
2004-09-03 19:57 ` Carl Riechers
0 siblings, 2 replies; 6+ messages in thread
From: Barbier, Renaud @ 2004-09-02 17:10 UTC (permalink / raw)
To: u-boot
I am trying to get U-boot on a custome ppc440gx board (CPU, 64MB RAM and the 2 gigabit port).
I have a problem, I am receiving this exception below. This happen when the EE bit is set in interrupt_init.
kgdb: handle_exception; trap [0xb00]
I am not sure what is the source of this exception. (decrementer should be 0x900)
Before that I was getting exception 0x500(external interrupt) and trace it to the UIC registers(polarity, trigger,...) being cleared (where?).
So I restore their value in interrrupt_init_cpu.
Note that I have run vxWorks and Linux on this board. I could believe I broke something.
-----Original Message-----
From: u-boot-users-admin@lists.sourceforge.net
[mailto:u-boot-users-admin at lists.sourceforge.net]On Behalf Of
philipv at cam.org
Sent: Thursday, September 02, 2004 3:29 PM
To: u-boot-users at lists.sourceforge.net
Subject: [U-Boot-Users] Booting in IPv6
Is there any support planned or in progress for booting in an IPv6 network?
Philip
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot-Users] ppc440gx
2004-09-02 17:10 [U-Boot-Users] ppc440gx Barbier, Renaud
@ 2004-09-03 13:25 ` Ralph Siemsen
2004-09-03 19:57 ` Carl Riechers
1 sibling, 0 replies; 6+ messages in thread
From: Ralph Siemsen @ 2004-09-03 13:25 UTC (permalink / raw)
To: u-boot
Barbier, Renaud (GE Infrastructure) wrote:
> kgdb: handle_exception; trap [0xb00]
>
> I am not sure what is the source of this exception. (decrementer should be 0x900)
>
> Before that I was getting exception 0x500(external interrupt) and trace it to the UIC registers(polarity, trigger,...) being cleared (where?).
> So I restore their value in interrrupt_init_cpu.
My numbers don't quite agree with yours... but I think you might be
seeing "Fixed Interval Timer" as the source of the exception. Sounds
like you are enabling interrupts before the handlers have been registered.
Just a guess, probably others know better...
-Ralph
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot-Users] ppc440gx
@ 2004-09-03 13:49 Barbier, Renaud
0 siblings, 0 replies; 6+ messages in thread
From: Barbier, Renaud @ 2004-09-03 13:49 UTC (permalink / raw)
To: u-boot
that is what I am looking for but TSR and TCR are always cleared. the interrupt should not come unless...
-----Original Message-----
From: u-boot-users-admin@lists.sourceforge.net
[mailto:u-boot-users-admin at lists.sourceforge.net]On Behalf Of Ralph
Siemsen
Sent: Friday, September 03, 2004 2:26 PM
To: Barbier, Renaud (GE Infrastructure)
Cc: u-boot-users at lists.sourceforge.net
Subject: Re: [U-Boot-Users] ppc440gx
Barbier, Renaud (GE Infrastructure) wrote:
> kgdb: handle_exception; trap [0xb00]
>
> I am not sure what is the source of this exception. (decrementer should be 0x900)
>
> Before that I was getting exception 0x500(external interrupt) and trace it to the UIC registers(polarity, trigger,...) being cleared (where?).
> So I restore their value in interrrupt_init_cpu.
My numbers don't quite agree with yours... but I think you might be
seeing "Fixed Interval Timer" as the source of the exception. Sounds
like you are enabling interrupts before the handlers have been registered.
Just a guess, probably others know better...
-Ralph
-------------------------------------------------------
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot-Users] ppc440gx
2004-09-02 17:10 [U-Boot-Users] ppc440gx Barbier, Renaud
2004-09-03 13:25 ` Ralph Siemsen
@ 2004-09-03 19:57 ` Carl Riechers
1 sibling, 0 replies; 6+ messages in thread
From: Carl Riechers @ 2004-09-03 19:57 UTC (permalink / raw)
To: u-boot
Make sure you have your SDRAM setting set properly.
Did you do your timing analysis? If your custom board
has the SDRAM very close to the processor you will
need to set your clock phase advance in the 45 to 70
degree range. My board would generate inconsistent
exceptions with the IBM recommended 90 phase advance
setting.
Good luck,
Carl
--- "Barbier, Renaud (GE Infrastructure)"
<Renaud.Barbier@ge.com> wrote:
> I am trying to get U-boot on a custome ppc440gx
> board (CPU, 64MB RAM and the 2 gigabit port).
>
> I have a problem, I am receiving this exception
> below. This happen when the EE bit is set in
> interrupt_init.
>
> kgdb: handle_exception; trap [0xb00]
>
> I am not sure what is the source of this exception.
> (decrementer should be 0x900)
>
> Before that I was getting exception 0x500(external
> interrupt) and trace it to the UIC
> registers(polarity, trigger,...) being cleared
> (where?).
> So I restore their value in interrrupt_init_cpu.
>
>
> Note that I have run vxWorks and Linux on this
> board. I could believe I broke something.
>
>
>
> -----Original Message-----
> From: u-boot-users-admin at lists.sourceforge.net
> [mailto:u-boot-users-admin at lists.sourceforge.net]On
> Behalf Of
> philipv at cam.org
> Sent: Thursday, September 02, 2004 3:29 PM
> To: u-boot-users at lists.sourceforge.net
> Subject: [U-Boot-Users] Booting in IPv6
>
>
>
> Is there any support planned or in progress for
> booting in an IPv6 network?
>
> Philip
>
>
>
>
>
-------------------------------------------------------
> This SF.Net email is sponsored by BEA Weblogic
> Workshop
> FREE Java Enterprise J2EE developer tools!
> Get your free copy of BEA WebLogic Workshop 8.1
> today.
>
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> _______________________________________________
> U-Boot-Users mailing list
> U-Boot-Users at lists.sourceforge.net
>
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>
>
>
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> Workshop
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> U-Boot-Users at lists.sourceforge.net
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot-Users] ppc440gx
@ 2004-09-10 17:08 Barbier, Renaud
2004-09-12 16:36 ` Wolfgang Denk
0 siblings, 1 reply; 6+ messages in thread
From: Barbier, Renaud @ 2004-09-10 17:08 UTC (permalink / raw)
To: u-boot
ok I think I found the problem I have with exception. It would appear that for some reason
the vector 0x500 gets assigned the UnkownException handler instead of external_interrupt
when I look at the end label in memory.
The last two values are the same and will be the offset to UnknownException
488: 03fc3bc8
48c: 03fc319c
588: 03fc3bc8
58c: 03fc319c
Any idea what may be broken here.?
-----Original Message-----
From: u-boot-users-admin@lists.sourceforge.net
[mailto:u-boot-users-admin at lists.sourceforge.net]On Behalf Of Barbier,
Renaud (GE Infrastructure)
Sent: Friday, September 03, 2004 2:49 PM
To: Ralph Siemsen
Cc: u-boot-users at lists.sourceforge.net
Subject: RE: [U-Boot-Users] ppc440gx
that is what I am looking for but TSR and TCR are always cleared. the interrupt should not come unless...
-----Original Message-----
From: u-boot-users-admin@lists.sourceforge.net
[mailto:u-boot-users-admin at lists.sourceforge.net]On Behalf Of Ralph
Siemsen
Sent: Friday, September 03, 2004 2:26 PM
To: Barbier, Renaud (GE Infrastructure)
Cc: u-boot-users at lists.sourceforge.net
Subject: Re: [U-Boot-Users] ppc440gx
Barbier, Renaud (GE Infrastructure) wrote:
> kgdb: handle_exception; trap [0xb00]
>
> I am not sure what is the source of this exception. (decrementer should be 0x900)
>
> Before that I was getting exception 0x500(external interrupt) and trace it to the UIC registers(polarity, trigger,...) being cleared (where?).
> So I restore their value in interrrupt_init_cpu.
My numbers don't quite agree with yours... but I think you might be
seeing "Fixed Interval Timer" as the source of the exception. Sounds
like you are enabling interrupts before the handlers have been registered.
Just a guess, probably others know better...
-Ralph
-------------------------------------------------------
This SF.Net email is sponsored by BEA Weblogic Workshop
FREE Java Enterprise J2EE developer tools!
Get your free copy of BEA WebLogic Workshop 8.1 today.
http://ads.osdn.com/?ad_id=5047&alloc_id=10808&op=click
_______________________________________________
U-Boot-Users mailing list
U-Boot-Users at lists.sourceforge.net
https://lists.sourceforge.net/lists/listinfo/u-boot-users
-------------------------------------------------------
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FREE Java Enterprise J2EE developer tools!
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot-Users] ppc440gx
2004-09-10 17:08 Barbier, Renaud
@ 2004-09-12 16:36 ` Wolfgang Denk
0 siblings, 0 replies; 6+ messages in thread
From: Wolfgang Denk @ 2004-09-12 16:36 UTC (permalink / raw)
To: u-boot
In message <45ABD2373C33C4459D42B40EC4F346F203200F1F@FTWMLVEM03.e2k.ad.ge.com> you wrote:
> ok I think I found the problem I have with exception. It would appear
> that for some reason
> the vector 0x500 gets assigned the UnkownException handler instead of
> external_interrupt
> when I look at the end label in memory.
> The last two values are the same and will be the offset to
> UnknownException
...
> Any idea what may be broken here.?
Bad SDRAM initialization causing memory errors?
Wolfgang Denk
--
Software Engineering: Embedded and Realtime Systems, Embedded Linux
Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd at denx.de
Nobody trips over mountains. It is the small pebble that causes you
to stumble. Pass all the pebbles in your path and you will find you
have crossed the mountain.
^ permalink raw reply [flat|nested] 6+ messages in thread
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2004-09-03 19:57 ` Carl Riechers
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