From: Yannic Moog <Y.Moog@phytec.de>
To: "festevam@gmail.com" <festevam@gmail.com>,
"uboot-imx@nxp.com" <uboot-imx@nxp.com>,
"sbabic@denx.de" <sbabic@denx.de>,
Teresa Remmet <T.Remmet@phytec.de>
Cc: "upstream@lists.phytec.de" <upstream@lists.phytec.de>,
"u-boot@lists.denx.de" <u-boot@lists.denx.de>,
Daniel Schultz <D.Schultz@phytec.de>,
Wadim Egorov <W.Egorov@phytec.de>
Subject: Re: [PATCH v2 6/6] board: phytec: phycore_imx8mp: Add 4000MTS RAM timings based on PCB rev
Date: Mon, 28 Aug 2023 12:33:44 +0000 [thread overview]
Message-ID: <41b9e008c60fc032edb0e8692015030382e13a18.camel@phytec.de> (raw)
In-Reply-To: <20230817085711.45339-7-t.remmet@phytec.de>
On Thu, 2023-08-17 at 10:57 +0200, Teresa Remmet wrote:
> Starting with PCB revision 3 we can safely make use of higher RAM
> frequency again. Make use of the EEPROM detection to determine the
> revision and use the updated RAM timings for new SoMs.
>
> Signed-off-by: Teresa Remmet <t.remmet@phytec.de>
Reviewed-by: Yannic Moog <y.moog@phytec.de>
Tested-by: Yannic Moog <y.moog@phytec.de>
> --
> Changes in v2:
> - Fix wrong RAM Timing values as pointed out by Yannic
> ---
> board/phytec/phycore_imx8mp/spl.c | 61
> +++++++++++++++++++++++++++++++
> 1 file changed, 61 insertions(+)
>
> diff --git a/board/phytec/phycore_imx8mp/spl.c
> b/board/phytec/phycore_imx8mp/spl.c
> index 49406f2eafad..d38f6368fe36 100644
> --- a/board/phytec/phycore_imx8mp/spl.c
> +++ b/board/phytec/phycore_imx8mp/spl.c
> @@ -46,6 +46,67 @@ void spl_dram_init(void)
> if (!ret)
> phytec_print_som_info(NULL);
>
> + ret = phytec_get_rev(NULL);
> + if (ret >= 3 && ret != PHYTEC_EEPROM_INVAL) {
> + dram_timing.ddrc_cfg[3].val = 0x1323;
> + dram_timing.ddrc_cfg[4].val = 0x1e84800;
> + dram_timing.ddrc_cfg[5].val = 0x7a0118;
> + dram_timing.ddrc_cfg[8].val = 0xc00307a3;
> + dram_timing.ddrc_cfg[9].val = 0xc50000;
> + dram_timing.ddrc_cfg[10].val = 0xf4003f;
> + dram_timing.ddrc_cfg[11].val = 0xf30000;
> + dram_timing.ddrc_cfg[14].val = 0x2028222a;
> + dram_timing.ddrc_cfg[15].val = 0x8083f;
> + dram_timing.ddrc_cfg[16].val = 0xe0e000;
> + dram_timing.ddrc_cfg[17].val = 0x12040a12;
> + dram_timing.ddrc_cfg[18].val = 0x2050f0f;
> + dram_timing.ddrc_cfg[19].val = 0x1010009;
> + dram_timing.ddrc_cfg[20].val = 0x502;
> + dram_timing.ddrc_cfg[21].val = 0x20800;
> + dram_timing.ddrc_cfg[22].val = 0xe100002;
> + dram_timing.ddrc_cfg[23].val = 0x120;
> + dram_timing.ddrc_cfg[24].val = 0xc80064;
> + dram_timing.ddrc_cfg[25].val = 0x3e8001e;
> + dram_timing.ddrc_cfg[26].val = 0x3207a12;
> + dram_timing.ddrc_cfg[28].val = 0x4a3820e;
> + dram_timing.ddrc_cfg[30].val = 0x230e;
> + dram_timing.ddrc_cfg[37].val = 0x799;
> + dram_timing.ddrc_cfg[38].val = 0x9141d1c;
> + dram_timing.ddrc_cfg[74].val = 0x302;
> + dram_timing.ddrc_cfg[83].val = 0x599;
> + dram_timing.ddrc_cfg[99].val = 0x302;
> + dram_timing.ddrc_cfg[108].val = 0x599;
> + dram_timing.ddrphy_cfg[66].val = 0x18;
> + dram_timing.ddrphy_cfg[75].val = 0x1e3;
> + dram_timing.ddrphy_cfg[77].val = 0x1e3;
> + dram_timing.ddrphy_cfg[79].val = 0x1e3;
> + dram_timing.ddrphy_cfg[145].val = 0x3e8;
> + dram_timing.fsp_msg[0].drate = 4000;
> + dram_timing.fsp_msg[0].fsp_cfg[1].val = 0xfa0;
> + dram_timing.fsp_msg[0].fsp_cfg[10].val = 0x3ff4;
> + dram_timing.fsp_msg[0].fsp_cfg[11].val = 0xf3;
> + dram_timing.fsp_msg[0].fsp_cfg[15].val = 0x3ff4;
> + dram_timing.fsp_msg[0].fsp_cfg[16].val = 0xf3;
> + dram_timing.fsp_msg[0].fsp_cfg[22].val = 0xf400;
> + dram_timing.fsp_msg[0].fsp_cfg[23].val = 0xf33f;
> + dram_timing.fsp_msg[0].fsp_cfg[28].val = 0xf400;
> + dram_timing.fsp_msg[0].fsp_cfg[29].val = 0xf33f;
> + dram_timing.fsp_msg[3].drate = 4000;
> + dram_timing.fsp_msg[3].fsp_cfg[1].val = 0xfa0;
> + dram_timing.fsp_msg[3].fsp_cfg[11].val = 0x3ff4;
> + dram_timing.fsp_msg[3].fsp_cfg[12].val = 0xf3;
> + dram_timing.fsp_msg[3].fsp_cfg[16].val = 0x3ff4;
> + dram_timing.fsp_msg[3].fsp_cfg[17].val = 0xf3;
> + dram_timing.fsp_msg[3].fsp_cfg[23].val = 0xf400;
> + dram_timing.fsp_msg[3].fsp_cfg[24].val = 0xf33f;
> + dram_timing.fsp_msg[3].fsp_cfg[29].val = 0xf400;
> + dram_timing.fsp_msg[3].fsp_cfg[30].val = 0xf33f;
> + dram_timing.ddrphy_pie[480].val = 0x465;
> + dram_timing.ddrphy_pie[481].val = 0xfa;
> + dram_timing.ddrphy_pie[482].val = 0x9c4;
> + dram_timing.fsp_table[0] = 4000;
> + }
> +
> out:
> ddr_init(&dram_timing);
> }
next prev parent reply other threads:[~2023-08-28 12:33 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-08-17 8:57 [PATCH v2 0/6] PHYTEC SoM detection for phyCORE-i.MX8MP Teresa Remmet
2023-08-17 8:57 ` [PATCH v2 1/6] board: phytec: Add common PHYTEC SoM detection Teresa Remmet
2023-08-28 12:32 ` Yannic Moog
2023-10-07 13:00 ` Fabio Estevam
2023-08-17 8:57 ` [PATCH v2 2/6] board: phytec: common: Add imx8m specific EEPROM detection support Teresa Remmet
2023-08-28 12:32 ` Yannic Moog
2023-08-17 8:57 ` [PATCH v2 3/6] board: phytec: phycore-imx8mp: Add EEPROM detection initialisation Teresa Remmet
2023-08-28 12:32 ` Yannic Moog
2023-08-17 8:57 ` [PATCH v2 4/6] board: phytec: phycore_imx8mp: Update 2GB RAM Timings Teresa Remmet
2023-08-28 12:33 ` Yannic Moog
2023-08-17 8:57 ` [PATCH v2 5/6] board: phytec: common: phytec_som_detection: Add helper for PCB revision Teresa Remmet
2023-08-28 12:33 ` Yannic Moog
2023-08-17 8:57 ` [PATCH v2 6/6] board: phytec: phycore_imx8mp: Add 4000MTS RAM timings based on PCB rev Teresa Remmet
2023-08-28 12:33 ` Yannic Moog [this message]
2023-08-24 11:52 ` [PATCH v2 0/6] PHYTEC SoM detection for phyCORE-i.MX8MP Fabio Estevam
2023-08-25 11:46 ` Yannic Moog
-- strict thread matches above, loose matches on Subject: below --
2023-10-16 11:51 [PATCH v2 6/6] board: phytec: phycore_imx8mp: Add 4000MTS RAM timings based on PCB rev sbabic
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