From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 56C06D2E015 for ; Wed, 23 Oct 2024 06:13:08 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id DB1EB8929F; Wed, 23 Oct 2024 08:13:06 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="LhcYGlqP"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id 8099E892CD; Wed, 23 Oct 2024 08:13:06 +0200 (CEST) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 03DC98929F for ; Wed, 23 Oct 2024 08:13:00 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=a-limaye@ti.com Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 49N6Cw6O033019; Wed, 23 Oct 2024 01:12:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1729663978; bh=YzPe/AfrbtOGyXjT96nkeDgNgWqJbvtLBQ5PbziSxNk=; h=Date:Subject:To:CC:References:From:In-Reply-To; b=LhcYGlqPaYKDedLcUdGw2uhOGJRksB9o5mZ9hrhfyWGRylgwcm9mINN1ds/Wha3Ly nkW0f2vQJ8dzoxg+2sOJaf6SbIJQqhw7G6/r8rO5KzvFiQ6SqRwDcJKtQmyLkB484L bw4A07pTtC4oIYORffoh7d0xxPTY2gqH6QM+X4UQ= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49N6CwsX002833; Wed, 23 Oct 2024 01:12:58 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Wed, 23 Oct 2024 01:12:58 -0500 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Wed, 23 Oct 2024 01:12:58 -0500 Received: from [172.24.227.91] (psdkl-workstation0.dhcp.ti.com [172.24.227.91]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 49N6CtfR080899; Wed, 23 Oct 2024 01:12:56 -0500 Message-ID: <41bee479-47cf-4ea4-b628-05d265bc2bbc@ti.com> Date: Wed, 23 Oct 2024 11:42:54 +0530 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/6] arm: dts: k3-j7200-r5-common: Add msmc clk to a72 node To: Neha Malcom Francis , , CC: , , , References: <20241017062911.2241167-1-a-limaye@ti.com> <20241017062911.2241167-2-a-limaye@ti.com> <9a5dc591-a5ca-4d53-9465-242986f4a62e@ti.com> Content-Language: en-US From: Aniket Limaye In-Reply-To: <9a5dc591-a5ca-4d53-9465-242986f4a62e@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On 17/10/24 16:00, Neha Malcom Francis wrote: > Hi Aniket > > On 17/10/24 11:59, Aniket Limaye wrote: >> From: Reid Tonking >> >> Define the MSMC clk in the a72 node > > The usage of MSMC and A72SS interchangeably in this series is confusing. > Could you expand on it in the cover letter why in J7200 this clock is > defined as part of the A72 node as opposed to devices that have MSMC as > a separate module altogether with its own clock (like J721S2 and J784S4)? Yeah sure. will elaborate in v2: The msmc clock frequency needs to be updated as per selected OPP (in PATCH 4). But we don't have a msmc node for j721e/j7200, unlike those in j721s2/j784s4. So we are defining the msmc clock in the a72_0 node, such that it's frequency can be updated along with core clock frequency when OPP_LOW config is selected. I am open to suggestions if this is not the right place for it. Thanks for the reviews! Regards, Aniket >> >> Signed-off-by: Reid Tonking >> Signed-off-by: Aniket Limaye >> --- >>   arch/arm/dts/k3-j7200-r5-common-proc-board.dts | 10 +++++----- >>   1 file changed, 5 insertions(+), 5 deletions(-) >> >> diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts >> b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts >> index f096b102793..759a1e83456 100644 >> --- a/arch/arm/dts/k3-j7200-r5-common-proc-board.dts >> +++ b/arch/arm/dts/k3-j7200-r5-common-proc-board.dts >> @@ -23,11 +23,11 @@ >>                   <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>, >>                   <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>; >>           resets = <&k3_reset 202 0>; >> -        clocks = <&k3_clks 61 1>, <&k3_clks 202 2>; >> -        clock-names = "gtc", "core"; >> -        assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, >> <&k3_clks 323 0>; >> -        assigned-clock-parents= <0>, <0>, <&k3_clks 323 2>; >> -        assigned-clock-rates = <2000000000>, <200000000>; >> +        clocks = <&k3_clks 61 1>, <&k3_clks 4 1>, <&k3_clks 202 2> ; >> +        clock-names = "gtc", "msmc", "core"; >> +        assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>, >> <&k3_clks 4 1>, <&k3_clks 323 0>; >> +        assigned-clock-parents= <0>, <0>, <0>, <&k3_clks 323 2>; >> +        assigned-clock-rates = <2000000000>, <200000000>, <1000000000>; >>           ti,sci = <&dmsc>; >>           ti,sci-proc-id = <32>; >>           ti,sci-host-id = <10>; >