[U-Boot-Users] Bug in AT91RM9200: icache not enabled!

[U-Boot-Users] Bug in AT91RM9200: icache not enabled!

[Steven Scholz]

Hi there,

while finding out why the loading of my FPGA takes so long with the latest CVS 
version of U-Boot I noticed that the icache for the AT91RM9200 is not enabled 
although icache_enable() is called in cpu/at91rm9200/start.S:

         /*
          * This does a lot more than just set up the memory, which
          * is why it's called lowlevelinit
          */
         bl      lowlevelinit /* in memsetup.S */
         bl      icache_enable;
    ...
         mrc     p15, 0, r0, c1, c0, 0
         /* Reset bit :Little Endian end fast bus mode */
         ldr     r3, =0xC0000080
         /* Set bit :Asynchronous clock mode, Not Fast Bus */
         ldr     r4, =0xC0000000
         bic     r0, r0, r3
         orr     r0, r0, r4
         /* write r0 in cp15 control register (cp15 r1) */
         mcr     p15, 0, r0, c1, c0, 0

The problem is that icache_enable() only works on bit 2 of CP15 Reg 1. But the 
important bit seems to be bit 12 judging by the AT91RM9200 User Manual page 49.

Looking at cpu/arm920t/start.S reveals that bit 12 is set:

         /*
          * disable MMU stuff and caches
          */
         mrc     p15, 0, r0, c1, c0, 0
         bic     r0, r0, #0x00002300     @ clear bits 13, 9:8 (--V- --RS)
         bic     r0, r0, #0x00000087     @ clear bits 7, 2:0 (B--- -CAM)
         orr     r0, r0, #0x00000002     @ set bit 2 (A) Align
 >>>>    orr     r0, r0, #0x00001000     @ set bit 12 (I) I-Cache
         mcr     p15, 0, r0, c1, c0, 0

So my suggestion is using the above code from cpu/arm920t/start.S for the 
AT91RM9200 for consistency in the ARM directories. Explicitly disabling MMU 
would not harm. And maybe explicitly enabling "Alignment Fault" would be a good 
thing as well.

And maybe we should even fix the functions dcache_{en,dis}able() and 
icache_{en,dis}able() in cpu/at91rm9200/cpu.c by introducing

-#define C1_IDC          (1<<2)  /* icache and/or dcache off/on */
+#define C1_DC           (1<<2)  /* dcache off/on */
+#define C1_IC           (1<<1)  /* icache off/on */

just like in cpu/arm920t/cpu.c.

Please comment on this. I am willing to sent appropriate patches.

Thanks a million!

-- 
Steven

[U-Boot-Users] Bug in AT91RM9200: icache not enabled!

[Steven Scholz]

Hi there,

> while finding out why the loading of my FPGA takes so long with the 
> latest CVS version of U-Boot I noticed that the icache for the 
> AT91RM9200 is not enabled although icache_enable() is called in 
> cpu/at91rm9200/start.S:
> 
>         /*
>          * This does a lot more than just set up the memory, which
>          * is why it's called lowlevelinit
>          */
>         bl      lowlevelinit /* in memsetup.S */
>         bl      icache_enable;
>    ...
> 
> The problem is that icache_enable() only works on bit 2 of CP15 Reg 1. 
> But the important bit seems to be bit 12 judging by the AT91RM9200 User 
> Manual page 49.

I am a bit confused right now! The function

void icache_enable(void)
{
     ulong reg;
     reg = read_p15_c1();
     cp_delay();
     reg |= C1_IC;
     write_p15_c1(reg);
}

from cpu/at91rm9200/cpu.c does not seem to work (at least when called from 
start.S). When I do

  mrc     p15, 0, r0, c1, c0, 0	@ read cp15 control register (cp15 r1) in r0
  orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
  mcr     p15, 0, r0, c1, c0, 0	@ write r0 in cp15 control register (cp15 r1)

which should be the same, it works ... :-(

Especially I dont understand why the C function would need a cp_delay() why the 
assembler code does not ...

--
Steven

[U-Boot-Users] Bug in AT91RM9200: icache not enabled!

[Steven Scholz]

Hi,

>>while finding out why the loading of my FPGA takes so long with the latest CVS 
>>version of U-Boot I noticed that the icache for the AT91RM9200 is not enabled 
>>although icache_enable() is called in cpu/at91rm9200/start.S:

>>Please comment on this. I am willing to sent appropriate patches.
> 
> Please send a patch so I can test how it works.

* Patch by Steven Scholz, 13 March 2005:
   fix cache enabling for AT91RM9200


Please remove the line

	orr     r0, r0, #0x00000004     @ set bit 3 (C) D-Cache

if we don't need the data cache for the AT91RM9200. I am not sure if they will 
help for CRCs or unzipping...

-- 
Steven
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[U-Boot-Users] Bug in AT91RM9200: icache not enabled!

[Wolfgang Denk]

In message <4234639D.9090607@imc-berlin.de> you wrote:
>
> * Patch by Steven Scholz, 13 March 2005:
>    fix cache enabling for AT91RM9200

Seems to work fine for me.

> Please remove the line
> 
> 	orr     r0, r0, #0x00000004     @ set bit 3 (C) D-Cache
> 
> if we don't need the data cache for the AT91RM9200. I am not sure if they will 
> help for CRCs or unzipping...

I don't see any obvious effect with or without  this  line  regarding
time needed for CRC or unzip. Why should we remove it?

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
Physician: One upon whom we set our hopes when ill and our dogs  when
well.                                                - Ambrose Bierce

[U-Boot-Users] Bug in AT91RM9200: icache not enabled!

[Steven Scholz]

Morning,

>>* Patch by Steven Scholz, 13 March 2005:
>>   fix cache enabling for AT91RM9200
> 
> Seems to work fine for me.

:o)

>>Please remove the line
>>
>>	orr     r0, r0, #0x00000004     @ set bit 3 (C) D-Cache
>>
>>if we don't need the data cache for the AT91RM9200. I am not sure if they will 
>>help for CRCs or unzipping...
> 
> I don't see any obvious effect with or without  this  line  regarding
> time needed for CRC or unzip. Why should we remove it?

Cause this bit is not set by arm920t/start.S either. Maybe for some reason?

Anyway, why has DCACHE no effect on CRC? It should though.

--
Steven

[U-Boot-Users] Bug in AT91RM9200: icache not enabled!

[Paugam Luc]

Dear Steven,

I saw your patch and tried it. Thanks for pointing out that I-Cache
wasn't enabled.

However, isn't it too dangerous to enable D-Cache too?
Because usually U-Boot recommends to disable it?

Regards - Luc

-----Original Message-----
From: u-boot-users-admin@lists.sourceforge.net
[mailto:u-boot-users-admin at lists.sourceforge.net] On Behalf Of Steven
Scholz
Sent: dimanche 13 mars 2005 17:00
To: u-boot-users at lists.sourceforge.net
Subject: Re: [U-Boot-Users] Bug in AT91RM9200: icache not enabled!

Hi,

>>while finding out why the loading of my FPGA takes so long with the
latest CVS 
>>version of U-Boot I noticed that the icache for the AT91RM9200 is not
enabled 
>>although icache_enable() is called in cpu/at91rm9200/start.S:

>>Please comment on this. I am willing to sent appropriate patches.
> 
> Please send a patch so I can test how it works.

* Patch by Steven Scholz, 13 March 2005:
   fix cache enabling for AT91RM9200


Please remove the line

	orr     r0, r0, #0x00000004     @ set bit 3 (C) D-Cache

if we don't need the data cache for the AT91RM9200. I am not sure if
they will 
help for CRCs or unzipping...

-- 
Steven

[U-Boot-Users] Bug in AT91RM9200: icache not enabled!

[Wolfgang Denk]

Dear Luc,

in message <1CFEB358338412458B21FAA0D78FE86D023CD734@rennsmail02.eu.thmulti.com> you wrote:
> 
> I saw your patch and tried it. Thanks for pointing out that I-Cache
> wasn't enabled.
> 
> However, isn't it too dangerous to enable D-Cache too?
> Because usually U-Boot recommends to disable it?

There is no such recommendation. There  is  only  a  comment  in  the
README  about  8xx/8260 systems (where D-cache cannot be enabled) and
those systems where the cache is user as storage for the initial data
(whereD-cache cannot be disabled).

Best regards,

Wolfgang Denk

-- 
Software Engineering:  Embedded and Realtime Systems,  Embedded Linux
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd at denx.de
There are two ways to write error-free programs. Only the  third  one
works.