From mboxrd@z Thu Jan  1 00:00:00 1970
From: Steven Scholz <steven.scholz@imc-berlin.de>
Date: Sun, 13 Mar 2005 16:40:18 +0100
Subject: [U-Boot-Users] Bug in AT91RM9200: icache not enabled!
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References: <42344819.4020103@imc-berlin.de>
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To: u-boot@lists.denx.de

Hi there,

> while finding out why the loading of my FPGA takes so long with the 
> latest CVS version of U-Boot I noticed that the icache for the 
> AT91RM9200 is not enabled although icache_enable() is called in 
> cpu/at91rm9200/start.S:
> 
>         /*
>          * This does a lot more than just set up the memory, which
>          * is why it's called lowlevelinit
>          */
>         bl      lowlevelinit /* in memsetup.S */
>         bl      icache_enable;
>    ...
> 
> The problem is that icache_enable() only works on bit 2 of CP15 Reg 1. 
> But the important bit seems to be bit 12 judging by the AT91RM9200 User 
> Manual page 49.

I am a bit confused right now! The function

void icache_enable(void)
{
     ulong reg;
     reg = read_p15_c1();
     cp_delay();
     reg |= C1_IC;
     write_p15_c1(reg);
}

from cpu/at91rm9200/cpu.c does not seem to work (at least when called from 
start.S). When I do

  mrc     p15, 0, r0, c1, c0, 0	@ read cp15 control register (cp15 r1) in r0
  orr	r0, r0, #0x00001000	@ set bit 12 (I) I-Cache
  mcr     p15, 0, r0, c1, c0, 0	@ write r0 in cp15 control register (cp15 r1)

which should be the same, it works ... :-(

Especially I dont understand why the C function would need a cp_delay() why the 
assembler code does not ...

--
Steven