[U-Boot-Users] Re: Bug in AT91RM9200: icache not enabled!

[Steven Scholz <steven.scholz@imc-berlin.de>]

Hi Eric,

thanks for your reply. Please include mailing list next time.

> I'm working on the same issue and had to modify cpu.c like on arm920 cpu
> and had to change in cpu/at91rm9200/start.s
> from :
>         mrc     p15, 0, r0, c1, c0, 0
>         /* Reset bit :Little Endian end fast bus mode */
>         ldr     r3, =0xC0000080
>         /* Set bit :Asynchronous clock mode, Not Fast Bus */
>         ldr     r4, =0xC0000000
>         bic     r0, r0, r3
>         orr     r0, r0, r4
>         /* write r0 in cp15 control register (cp15 r1) */
>         mcr     p15, 0, r0, c1, c0, 0
> 
> to :
> 	ldr	r0, =0xc000507C
>         @ write r0 in cp15 control register (cp15 r1)
>         mcr      p15, 0, r0, c1, c0,0

Yeah. Pretty much like arm920t.

> 
> & to remove the call to icache_enable in after lowlevelinit (no more
> necessary as the icache is enabled by the previous change.
> 
> in order to get both cache activated.

So you realy have both data and instruction cache enable in U-Boot?

--

Steven