[U-Boot-Users] Re: Bug in AT91RM9200: icache not enabled!

[U-Boot-Users] Re: Bug in AT91RM9200: icache not enabled!

[Steven Scholz]

Hi Eric,

thanks for your reply. Please include mailing list next time.

> I'm working on the same issue and had to modify cpu.c like on arm920 cpu
> and had to change in cpu/at91rm9200/start.s
> from :
>         mrc     p15, 0, r0, c1, c0, 0
>         /* Reset bit :Little Endian end fast bus mode */
>         ldr     r3, =0xC0000080
>         /* Set bit :Asynchronous clock mode, Not Fast Bus */
>         ldr     r4, =0xC0000000
>         bic     r0, r0, r3
>         orr     r0, r0, r4
>         /* write r0 in cp15 control register (cp15 r1) */
>         mcr     p15, 0, r0, c1, c0, 0
> 
> to :
> 	ldr	r0, =0xc000507C
>         @ write r0 in cp15 control register (cp15 r1)
>         mcr      p15, 0, r0, c1, c0,0

Yeah. Pretty much like arm920t.

> 
> & to remove the call to icache_enable in after lowlevelinit (no more
> necessary as the icache is enabled by the previous change.
> 
> in order to get both cache activated.

So you realy have both data and instruction cache enable in U-Boot?

--

Steven

[U-Boot-Users] Re: Bug in AT91RM9200: icache not enabled!

[Steven Scholz]

Hi Eric,

>>     ldr    r0, =0xc000507C
>>         @ write r0 in cp15 control register (cp15 r1)
>>         mcr      p15, 0, r0, c1, c0,0

What is that "Round robin replacement" (Bit 14) for?

--
Steven

[U-Boot-Users] Re: Bug in AT91RM9200: icache not enabled!

[Eric BENARD / Free]

Steven Scholz a ?crit :
> thanks for your reply. Please include mailing list next time.
> 
sorry, I'm reading through gmane and I'm not subscribed to the list.
> 
> So you realy have both data and instruction cache enable in U-Boot?
> 
yes, at least I think so as kernel uncompressing is really faster when
using this setting.

Just add CFG_CMD_CACHE to #define CONFIG_COMMANDS in your
include/configs/x.h file
and you will be able to get cache informations :
=> icache
Instruction Cache is ON
=> dcache
Data (writethrough) Cache is ON

The strange thing is that :
- it's possible to turn icache off but not to enable it again
- it's not possible to turn dcache off.

=> icache off
Instruction Cache is OFF
=> icache on
Instruction Cache is OFF
=> dcache off
Data (writethrough) Cache is ON
=> dcache on
Data (writethrough) Cache is ON

I'm trying to understand why.

Eric

[U-Boot-Users] Re: Bug in AT91RM9200: icache not enabled!

[Steven Scholz]

Hi Eric,

> The strange thing is that :
> - it's possible to turn icache off but not to enable it again
> - it's not possible to turn dcache off.
> 
> => icache off
> Instruction Cache is OFF
> => icache on
> Instruction Cache is OFF
> => dcache off
> Data (writethrough) Cache is ON
> => dcache on
> Data (writethrough) Cache is ON

I am seeing the same. And I dont understand it rigth now.

--
Steven