From mboxrd@z Thu Jan  1 00:00:00 1970
From: Pantelis Antoniou <panto@intracom.gr>
Date: Mon, 25 Apr 2005 18:18:36 +0300
Subject: [U-Boot-Users] struct NS16550 {...} __attribute__ ((packed))
 at ns16550.h
In-Reply-To: <20050425145653.E9CCDC1510@atlas.denx.de>
References: <20050425145653.E9CCDC1510@atlas.denx.de>
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Wolfgang Denk wrote:
> In message <001501c5499f$f5364750$1780a8c0@art> you wrote:
> 
>>>If this is really true, then there is either bug in GCC or in the code.
>>>If I code a 32 bit access the compiler must not use any other accesses.
>>
>>If you use __attribute__ ((packed)), you are telling the compiler you have
>>an unaligned data structure (e.g. longs not by-4 aligned).  Therefore, GCC
>>will always reassemble the 32-bit value from byte accesses.
> 
> 
> You are wrong, with both of your statements.
> 
> -> cat foo.c
> struct foo {
>         unsigned long foo1;
>         unsigned long foo2;
>         unsigned long foo3;
> } __attribute__ ((packed));
> 
> unsigned long dummy (struct foo *p)
> {
>         return (p->foo1 + p->foo2 + p->foo3);
> }
> 
> 
> Test 1: PowerPC:
> 
> -> ppc_8xx-gcc -O -S foo.c
> -> cat foo.s
> ...
> dummy:
>         mr 9,3
>         lwz 3,0(3)
>         lwz 0,4(9)
>         add 3,3,0
>         lwz 0,8(9)
>         add 3,3,0
>         blr
> 
> 
> Test 2: MIPS:
> 
> -> mips_4KC-gcc -O -S foo.c
> -> cat foo.s
> ...
> dummy:
>         .frame  $sp,0,$31               # vars= 0, regs= 0/0, args= 0, extra= 0
>         .mask   0x00000000,0
>         .fmask  0x00000000,0
>         .set    noreorder
>         .cpload $25
>         .set    reorder
>         ulw     $2,0($4)
>         ulw     $3,4($4)
>         #nop
>         addu    $2,$2,$3
>         ulw     $3,8($4)
>         .set    noreorder
>         .set    nomacro
>         j       $31
>         addu    $2,$2,$3
>         .set    macro
>         .set    reorder
> 
> 
> As you can see, GCC alway uses plain word accesses (32 bit).
> 
> 
> 

Not on ARM it does not.

> 
> Best regards,
> 
> Wolfgang Denk
> 

Both PPC & MIPS can do proper unalligned load/stores (or fault to
an exception).

ARM (silently) does the wrong thing i.e. masks out the lower 2 bits.

So gcc on ARM generates byte load/stores.

Regards

Pantelis