[U-Boot-Users] PPC 440GX ECC SDRAM configuration from U-Boot

[Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>]

Chris Love wrote:
> We have U-Boot (& Linux) running on a custom board featuring a PPC
> 440GX.  For now we've been happy enough to get SDRAM configured and
> working (no SPD eeproms), but eventually have to tackle the issue of
> enabling ECC.
> 
> Per the application note from AMCC this will involve writing the entire
> memory array with valid or dummy data (with ECC enabled but not
> checking).  With code executing from flash, the time to iterate through
> all of memory and zero it out is pretty substantial.  The complete setup
> process involves changing other SDRAM configuration registers at various
> steps, implying that SDRAM is getting enabled and disabled (precluding
> doing this on the fly after U-Boot has relocated).
> 
> One thought here is to copy a SDRAM zeroing routine into internal SRAM
> (above the initial stack and global data) and execute from there.
> 
> Has anyone else tried to tackle ECC for the 440GX, and is this a
> reasonable approach to try?  Any other suggestions for someone
> relatively new to the land of PPC assembly code?
> 
> Thanks in advance,
> 
> 	Chris
> --
> Chris Love           // Continuous Computing
> chris.love at ccpu.com // http://www.ccpu.com

I have not used the 440gx, but I presume it implements the dcbz 
instruciton "Data Cache Block Set to Zero".  Loop through the cache 
blocks with this instruction... it has many benefits over a "normal" 
zeroing loop...
* Smaller loop count since you only need one instruction per cache line
     (32(?) bytes) rather than per 4-byte word.
* No memory read operation from SDRAM (a Good Thing when you are
     initializing EDC ;-).
* Burst writes when the cache line is flushed out to SDRAM... another
     major win.

You will be amazed at the speed difference.  You should be able to run 
with instruction caches enabled too, which should help substantially, 
perhaps amazingly.

gvb