[U-Boot-Users] PPC 440GX ECC SDRAM configuration from U-Boot

[U-Boot-Users] PPC 440GX ECC SDRAM configuration from U-Boot

[Chris Love]

We have U-Boot (& Linux) running on a custom board featuring a PPC
440GX.  For now we've been happy enough to get SDRAM configured and
working (no SPD eeproms), but eventually have to tackle the issue of
enabling ECC.

Per the application note from AMCC this will involve writing the entire
memory array with valid or dummy data (with ECC enabled but not
checking).  With code executing from flash, the time to iterate through
all of memory and zero it out is pretty substantial.  The complete setup
process involves changing other SDRAM configuration registers at various
steps, implying that SDRAM is getting enabled and disabled (precluding
doing this on the fly after U-Boot has relocated).

One thought here is to copy a SDRAM zeroing routine into internal SRAM
(above the initial stack and global data) and execute from there.

Has anyone else tried to tackle ECC for the 440GX, and is this a
reasonable approach to try?  Any other suggestions for someone
relatively new to the land of PPC assembly code?

Thanks in advance,

	Chris
--
Chris Love           // Continuous Computing
chris.love at ccpu.com // http://www.ccpu.com

[U-Boot-Users] PPC 440GX ECC SDRAM configuration from U-Boot

[Barbier, Renaud]

I too have ECC and have not solved complexly the problem.
So far it takes about 6-7s to initialize 512MB. Hence, 12-14s for 1GB.
The method I use is two lines of assembly code in the loop. My theory is that should run from the pipeline.


program_myecc:
    mtctr r3
    lis r7, 0xeeee
    ori r7, r7, 0xeeee
    lis r4, 0
    ori r4, r4, 0
zeroLoop:
    stwu r7, 8(r4)
    bdnz zeroLoop
    blr


This is a 32-bit store with update.

However, this is still not the fastest you can get.


Under vxWorks, I allocated (malloc) a big amount of memory (384MB) and bzero it.
I calculated it should take less than 2s to burn 512MB.
In this case vxWorks uses both the I and D cache. 




-----Original Message-----
From: u-boot-users-admin@lists.sourceforge.net
[mailto:u-boot-users-admin at lists.sourceforge.net]On Behalf Of Chris Love
Sent: Friday, May 27, 2005 1:34 AM
To: u-boot-users at lists.sourceforge.net
Cc: Chris Love
Subject: [U-Boot-Users] PPC 440GX ECC SDRAM configuration from U-Boot


We have U-Boot (& Linux) running on a custom board featuring a PPC
440GX.  For now we've been happy enough to get SDRAM configured and
working (no SPD eeproms), but eventually have to tackle the issue of
enabling ECC.

Per the application note from AMCC this will involve writing the entire
memory array with valid or dummy data (with ECC enabled but not
checking).  With code executing from flash, the time to iterate through
all of memory and zero it out is pretty substantial.  The complete setup
process involves changing other SDRAM configuration registers at various
steps, implying that SDRAM is getting enabled and disabled (precluding
doing this on the fly after U-Boot has relocated).

One thought here is to copy a SDRAM zeroing routine into internal SRAM
(above the initial stack and global data) and execute from there.

Has anyone else tried to tackle ECC for the 440GX, and is this a
reasonable approach to try?  Any other suggestions for someone
relatively new to the land of PPC assembly code?

Thanks in advance,

	Chris
--
Chris Love           // Continuous Computing
chris.love at ccpu.com // http://www.ccpu.com


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[U-Boot-Users] PPC 440GX ECC SDRAM configuration from U-Boot

[Jerry Van Baren]

Chris Love wrote:
> We have U-Boot (& Linux) running on a custom board featuring a PPC
> 440GX.  For now we've been happy enough to get SDRAM configured and
> working (no SPD eeproms), but eventually have to tackle the issue of
> enabling ECC.
> 
> Per the application note from AMCC this will involve writing the entire
> memory array with valid or dummy data (with ECC enabled but not
> checking).  With code executing from flash, the time to iterate through
> all of memory and zero it out is pretty substantial.  The complete setup
> process involves changing other SDRAM configuration registers at various
> steps, implying that SDRAM is getting enabled and disabled (precluding
> doing this on the fly after U-Boot has relocated).
> 
> One thought here is to copy a SDRAM zeroing routine into internal SRAM
> (above the initial stack and global data) and execute from there.
> 
> Has anyone else tried to tackle ECC for the 440GX, and is this a
> reasonable approach to try?  Any other suggestions for someone
> relatively new to the land of PPC assembly code?
> 
> Thanks in advance,
> 
> 	Chris
> --
> Chris Love           // Continuous Computing
> chris.love at ccpu.com // http://www.ccpu.com

I have not used the 440gx, but I presume it implements the dcbz 
instruciton "Data Cache Block Set to Zero".  Loop through the cache 
blocks with this instruction... it has many benefits over a "normal" 
zeroing loop...
* Smaller loop count since you only need one instruction per cache line
     (32(?) bytes) rather than per 4-byte word.
* No memory read operation from SDRAM (a Good Thing when you are
     initializing EDC ;-).
* Burst writes when the cache line is flushed out to SDRAM... another
     major win.

You will be amazed at the speed difference.  You should be able to run 
with instruction caches enabled too, which should help substantially, 
perhaps amazingly.

gvb