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From: Scott McNutt <smcnutt@psyent.com>
To: u-boot@lists.denx.de
Subject: [U-Boot-Users] CFI, saveenv Flash no Erased
Date: Mon, 15 Aug 2005 13:04:00 -0400	[thread overview]
Message-ID: <4300CB00.5050503@psyent.com> (raw)
In-Reply-To: <42FD2928.2090605@orkun.us>

Hi Tolunay,

Tolunay Orkun wrote:
> The timeout check is not correct in the current code.

As it turns out, this is a hardware issue, _not_ a software bug WRT
to my earlier post. It's related to using the toggle bit with the Nios
avalon bus (as described below). I hacked up some code to use DQ7
polling for erase/write status checking and everything works just fine.

The problem is bus-related: the Nios avalon bus always fetches 32-bits
from a memory peripheral, period .. regardless of the physical device
size. So, an 8-bit cpu read, results in 4 x 8-bit external bus cycles,
but only the first 8-bit read is delivered to the cpu core.

As you may well guess, the toggle bit transitions like this:
0 -> 1 -> 0 -> 1 for each 8-bit CPU read. So, the CPU never sees the
toggle bit change state -- it always gets the state from the first 8-bit
access. (Yikes!)

Anyway, that's what is happening. I'm not sure if there are any other
bus architectures that behave this way. But I'd like to hear what others
have to say WRT a compile time option to use DQ7 polling vs. toggle bit.
I'd be happy to work on such a patch.

Please don't tell me to fix the Nios-II external bus -- I have no
control over it-- and I still have a headache from tracking this issue
down ;-)

Best Regards,
--Scott

      parent reply	other threads:[~2005-08-15 17:04 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2005-08-12 18:24 [U-Boot-Users] CFI, saveenv Flash no Erased Scott McNutt
2005-08-12 22:56 ` Tolunay Orkun
2005-08-12 23:13   ` Wolfgang Denk
2005-08-15 17:04   ` Scott McNutt [this message]

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