From mboxrd@z Thu Jan  1 00:00:00 1970
From: Steven Scholz <steven.scholz@imc-berlin.de>
Date: Wed, 24 Aug 2005 10:38:32 +0200
Subject: [U-Boot-Users] AT91RM9200 Errata (Was: CSB637 support - big bug..)
In-Reply-To: <47F3F98010FF784EBEE6526EAAB078D119ED5B@tq-mailsrv.tq-net.de>
References: <47F3F98010FF784EBEE6526EAAB078D119ED5B@tq-mailsrv.tq-net.de>
Message-ID: <430C3208.1020903@imc-berlin.de>
List-Id: <u-boot.lists.denx.de>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
To: u-boot@lists.denx.de

Martin,

> A clock rate > 180 MHz could be problematic. According errata 42 
> (AC Characteristics: PLL Frequency Limitation), in AT91RM9200 errata 
> sheet (doc6015) the PLL is limited to 180 MHz. We already had problems 
> with this bug (with about 10%-15% of the CPUs). After configuring the
> PLL for 179 MHz no errors occour any mor (before we used 207 MHz).

Which errors and problems did you encounter?

--
Steven