[U-Boot-Users] Bug in AT91RM9200.h

[U-Boot-Users] Bug in AT91RM9200.h

[Steven Scholz]

Guys,

A while ago I sent the following the the linux arm ML. I am sure this
applies to U-Boot as well!

> I just noticed the following:
> 
> in incluse/asm-arm/mach-at91rm9200/AT91RM9200.h
> 
> #define AT91C_SMC2_DBW        (0x1 << 13) // (SMC2) Data Bus Width
> 
> and drivers/pcmcia/at91_cf.c uses code like
> 
>     csr &= ~AT91C_SMC2_DBW;
> 
> BUT:
> 
> According to the User Man the "DBW: Data Bus Width" field is _TWO_ bits.
> Thus it should be
> 
> #define AT91C_SMC2_DBW        (0x3 << 13) // (SMC2) Data Bus Width

So please apply this trivial.

* Fix define in AT91RM9200.h
  Patch by Steven Scholz, 10 Oct 2005

--
Steven

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[U-Boot-Users] Bug in AT91RM9200.h

[Steven Scholz]

Ladies,

there's another wrong define in AT91RM9200.

According the (my) User Man the RWHOLD field of SMC_CSR0..SMC_CSR7
starts at bit 28. Thus

#define AT91C_SMC2_RWHOLD               ((unsigned int) 0x7 << 29) /*
(SMC2) Read and Write Signal Hold Time */

is rubbish!

So please apply this trivial patch instead if my previous one:

* Fix defines AT91C_SMC2_DBW and AT91C_SMC2_RWHOLD in AT91RM9200.h
  Patch by Steven Scholz, 10 Oct 2005

(Machine generate header file - ha, ha!)

--
Steven

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