From mboxrd@z Thu Jan 1 00:00:00 1970 From: Steven Scholz Date: Mon, 10 Oct 2005 14:33:38 +0200 Subject: [U-Boot-Users] Bug in AT91RM9200.h In-Reply-To: <434A5D2A.6070906@imc-berlin.de> References: <42F82884.9090500@billgatliff.com> <42FC666D.6060704@imc-berlin.de> <434A5D2A.6070906@imc-berlin.de> Message-ID: <434A5FA2.2070806@imc-berlin.de> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Ladies, there's another wrong define in AT91RM9200. According the (my) User Man the RWHOLD field of SMC_CSR0..SMC_CSR7 starts at bit 28. Thus #define AT91C_SMC2_RWHOLD ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */ is rubbish! So please apply this trivial patch instead if my previous one: * Fix defines AT91C_SMC2_DBW and AT91C_SMC2_RWHOLD in AT91RM9200.h Patch by Steven Scholz, 10 Oct 2005 (Machine generate header file - ha, ha!) -- Steven -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: at91rm9200.h.patch Url: http://lists.denx.de/pipermail/u-boot/attachments/20051010/e0933ea8/attachment.txt