From mboxrd@z Thu Jan 1 00:00:00 1970 From: S. Egbert Date: Thu, 09 Feb 2006 00:35:49 -0800 Subject: [U-Boot-Users] Xilinx ML403/PPC U-Boot support In-Reply-To: <43EADCC3.7090208@xilinx.com> References: <43D9E2AB.5020108@sbcglobal.net> <43DEFF49.9090909@xilinx.com> <17386.45657.426834.355460@waldo.lisle.iphase.com> <43EAD639.7000005@sbcglobal.net> <43EADCC3.7090208@xilinx.com> Message-ID: <43EAFEE5.10306@sbcglobal.net> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Peter Ryser wrote: > >> Careful. ML403 reference design (as-is) is not using the Xilinx option >> of using side-by-side data access (32-bit fetch out of a single 16-bit >> flash), so XIP (execution in place) is evidently NOT supported in ML403. >> However, I had a new bit file built with side-by-side data access >> enabled, but haven't yet execute out of flash (no need because ML403 has >> a big memory.) But it correctly fetches 32-bit now. Ping me in a week >> on my progress with XIP and flash. >> > Hmm, why do you need that? The ML403 has two flash chips and with that > allows 32 bit wide accesses. That allows you to access the whole flash > space and should give you much better performance than executing out of > a 16 bit wide flash. > Brain fart. My ML403-derived board dropped only one flash chip down to one.... Please disregard note of side-by-side data fetch and ML403. This is not applicable toward ML403 reference design. XIP SHOULD BE possible out of linear flash, however, time is saved in the long run if you preload it into DDR SDRAM firstly. True on the better execution performance using two flash chips BUT no need for XIP here on my part. S. Egbert