From: Jason Rush <jarush@gmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH v2 0/3] cadence-quadspi: Fix issues with non 32bit aligned accesses
Date: Mon, 15 Jan 2018 07:47:57 -0600 [thread overview]
Message-ID: <43c8c965-91c5-14ec-df95-4fea4c022750@gmail.com> (raw)
In-Reply-To: <7f6a5bdc-3941-86bb-2ad4-b563ab5d3a48@de.pepperl-fuchs.com>
On 1/15/2018 6:01 AM, Simon Goldschmidt wrote:
>
> Pepperl+Fuchs GmbH, Mannheim
> Geschaeftsfuehrer/Managing Directors: Dr.-Ing. Gunther Kegel (Vors./CEO), Werner Guthier, Mehmet Hatiboglu
> Vorsitzender des Aufsichtsrats/Chairman of the supervisory board: Claus Michael
> Registergericht/Register Court: AG Mannheim HRB 4713
> On 15.01.2018 12:45, Marek Vasut wrote:
>> On 01/15/2018 12:36 PM, Vignesh R wrote:
>>> Marek,
>>>
>>> On 09-Jan-18 6:49 PM, Vignesh R wrote:
>>>> This series reverts use of bounce_buf.c for non-DMA related alignment
>>>> restriction and replaces it with local bounce buffer to handle problems
>>>> with non 32 bit aligned writes on TI platforms.
>>>> Based on top of Jason's series:
>>>> https://patchwork.ozlabs.org/cover/856431/
>>>>
>>>> Tested on K2G EVM.
>>>>
>>> Could you ack this series, if you are okay with the changes?
>>>
>>> Jagan,
>>> Could you pick this up(along with the above dependent patches) for
>>> 2018.03 once Marek's Ack is in place?
>>>
>> Acked-by: Marek Vasut <marex@denx.de>
>>
>> although you should get ack from Jason and Simon instead, those matter.
>>
>
> Acked-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com>
>
> If that "Simon" above was me :-) I thought ack was sent by maintainers and TB by me, sorry.
>
> Simon
>
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Looks good to me. Thanks Vignesh.
Reviewed-by: Jason Rush <jarush@gmail.com>
Acked-by: Jason Rush <jarush@gmail.com>
next prev parent reply other threads:[~2018-01-15 13:47 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-01-09 13:19 [U-Boot] [PATCH v2 0/3] cadence-quadspi: Fix issues with non 32bit aligned accesses Vignesh R
2018-01-09 13:19 ` [U-Boot] [PATCH v2 1/3] Revert "spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible" Vignesh R
2018-01-09 13:19 ` [U-Boot] [PATCH v2 2/3] Revert "spi: cadence_qspi_apb: Use 32 bit indirect write " Vignesh R
2018-01-09 13:19 ` [U-Boot] [PATCH v2 3/3] spi: cadence_qspi_apb: Make flash writes 32 bit aligned Vignesh R
2018-01-15 11:36 ` [U-Boot] [PATCH v2 0/3] cadence-quadspi: Fix issues with non 32bit aligned accesses Vignesh R
2018-01-15 11:45 ` Marek Vasut
2018-01-15 12:01 ` Simon Goldschmidt
2018-01-15 13:47 ` Jason Rush [this message]
2018-01-23 8:12 ` Simon Goldschmidt
2018-01-23 8:45 ` Jagan Teki
2018-01-23 9:02 ` Vignesh R
2018-01-23 9:07 ` Jagan Teki
2018-01-23 9:16 ` Vignesh R
2018-01-23 9:24 ` Jagan Teki
2018-01-23 9:26 ` Simon Goldschmidt
2018-01-23 9:31 ` Jagan Teki
2018-01-23 10:05 ` Vignesh R
-- strict thread matches above, loose matches on Subject: below --
2018-01-10 15:33 Goldschmidt Simon
2018-01-10 15:39 ` Marek Vasut
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