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([2a01:e0a:3cb:7bb0:ed29:9eea:a05:44fd]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ab6e4a0000dsm1062036666b.89.2025.02.05.01.27.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Feb 2025 01:27:06 -0800 (PST) Message-ID: <445a0c31-5a18-42e7-bb95-e380437d57f4@linaro.org> Date: Wed, 5 Feb 2025 10:27:04 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/6] meminfo: add memory details for armv8 To: Ilias Apalodimas , xypron.glpk@gmx.de, trini@konsulko.com Cc: Alexey Brodkin , Eugeniy Paltsev , Caleb Connolly , Neil Armstrong , Sumit Garg , Huan Wang , Angelo Dureghello , Thomas Chou , Rick Chen , Leo , Marek Vasut , Nobuhiro Iwamatsu , Max Filippov , Sughosh Ganu , Simon Glass , =?UTF-8?Q?Pierre-Cl=C3=A9ment_Tosi?= , Sam Protsenko , Peng Fan , Richard Henderson , Sam Edwards , Peter Hoyes , Andre Przywara , Patrick Rudolph , Sam Day , Mayuresh Chitale , Mattijs Korpershoek , Stefan Roese , Jagan Teki , Alex Shumsky , Jiaxun Yang , Joshua Watt , Evgeny Bachinin , Rasmus Villemoes , Michal Simek , Christian Marangi , Jonas Jelonek , uboot-snps-arc@synopsys.com, u-boot@lists.denx.de, u-boot-qcom@groups.io References: <20250205071714.635518-1-ilias.apalodimas@linaro.org> <20250205071714.635518-2-ilias.apalodimas@linaro.org> Content-Language: en-US From: Jerome Forissier In-Reply-To: <20250205071714.635518-2-ilias.apalodimas@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Mailman-Approved-At: Wed, 05 Feb 2025 14:15:26 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean On 2/5/25 08:16, Ilias Apalodimas wrote: > Upcoming patches are mapping memory with RO, RW^X etc permsissions. > Fix the meminfo command to display them properly > > Acked-by: Jerome Forissier > Signed-off-by: Ilias Apalodimas > --- > arch/arm/cpu/armv8/cache_v8.c | 26 +++++++++++++++++++++++--- > arch/arm/include/asm/armv8/mmu.h | 2 ++ > cmd/meminfo.c | 5 +++++ > 3 files changed, 30 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c > index 5d6953ffedd1..c4b3da4a8da7 100644 > --- a/arch/arm/cpu/armv8/cache_v8.c > +++ b/arch/arm/cpu/armv8/cache_v8.c > @@ -421,7 +421,7 @@ static int count_ranges(void) > return count; > } > > -#define ALL_ATTRS (3 << 8 | PMD_ATTRINDX_MASK) > +#define ALL_ATTRS (3 << 8 | PMD_ATTRMASK) > #define PTE_IS_TABLE(pte, level) (pte_type(&(pte)) == PTE_TYPE_TABLE && (level) < 3) > > enum walker_state { > @@ -568,6 +568,20 @@ static void pretty_print_table_attrs(u64 pte) > static void pretty_print_block_attrs(u64 pte) > { > u64 attrs = pte & PMD_ATTRINDX_MASK; > + u64 perm_attrs = pte & PMD_ATTRMASK; > + char mem_attrs[16] = { 0 }; 11 is enough is seems? > + int cnt = 0; > + > + if (perm_attrs & PTE_BLOCK_PXN) > + cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "PXN "); > + if (perm_attrs & PTE_BLOCK_UXN) > + cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "UXN "); > + if (perm_attrs & PTE_BLOCK_RO) > + cnt += snprintf(mem_attrs + cnt, sizeof(mem_attrs) - cnt, "RO"); > + if (!mem_attrs[0]) > + snprintf(mem_attrs, sizeof(mem_attrs), "RWX "); > + > + printf(" | %-10s", mem_attrs); > > switch (attrs) { > case PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE): > @@ -613,6 +627,7 @@ static void print_pte(u64 pte, int level) > { > if (PTE_IS_TABLE(pte, level)) { > printf(" %-5s", "Table"); > + printf(" %-12s", "|"); > pretty_print_table_attrs(pte); > } else { > pretty_print_pte_type(pte); > @@ -642,9 +657,9 @@ static bool pagetable_print_entry(u64 start_attrs, u64 end, int va_bits, int lev > > printf("%*s", indent * 2, ""); > if (PTE_IS_TABLE(start_attrs, level)) > - printf("[%#011llx]%14s", _addr, ""); > + printf("[%#016llx]%19s", _addr, ""); > else > - printf("[%#011llx - %#011llx]", _addr, end); > + printf("[%#016llx - %#016llx]", _addr, end); > > printf("%*s | ", (3 - level) * 2, ""); > print_pte(start_attrs, level); > @@ -1112,3 +1127,8 @@ void __weak enable_caches(void) > icache_enable(); > dcache_enable(); > } > + > +void arch_dump_mem_attrs(void) > +{ > + dump_pagetable(gd->arch.tlb_addr, get_tcr(NULL, NULL)); > +} > diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h > index 0ab681c893d3..6af8cd111a44 100644 > --- a/arch/arm/include/asm/armv8/mmu.h > +++ b/arch/arm/include/asm/armv8/mmu.h > @@ -66,6 +66,7 @@ > #define PTE_BLOCK_NG (1 << 11) > #define PTE_BLOCK_PXN (UL(1) << 53) > #define PTE_BLOCK_UXN (UL(1) << 54) > +#define PTE_BLOCK_RO (UL(1) << 7) > > /* > * AttrIndx[2:0] > @@ -75,6 +76,7 @@ > #define PMD_ATTRMASK (PTE_BLOCK_PXN | \ > PTE_BLOCK_UXN | \ > PMD_ATTRINDX_MASK | \ > + PTE_BLOCK_RO | \ > PTE_TYPE_VALID) > > /* > diff --git a/cmd/meminfo.c b/cmd/meminfo.c > index 5e83d61c2dd3..3915e2bbb268 100644 > --- a/cmd/meminfo.c > +++ b/cmd/meminfo.c > @@ -15,6 +15,10 @@ > > DECLARE_GLOBAL_DATA_PTR; > > +void __weak arch_dump_mem_attrs(void) > +{ > +} > + > static void print_region(const char *name, ulong base, ulong size, ulong *uptop) > { > ulong end = base + size; > @@ -54,6 +58,7 @@ static int do_meminfo(struct cmd_tbl *cmdtp, int flag, int argc, > > puts("DRAM: "); > print_size(gd->ram_size, "\n"); > + arch_dump_mem_attrs(); > > if (!IS_ENABLED(CONFIG_CMD_MEMINFO_MAP)) > return 0;