[U-Boot-Users] [PATCH] fix incorrect bus clk of 83xx

[U-Boot-Users] [PATCH] fix incorrect bus clk of 83xx

[Liu Dave-r63238]

All,

The gd->bus_clk of 83xx should be csb_clk, not libu_clk,
If it don't be changed, will make the timer incorrect.

CHANGELOG:
* fix incorrect gd->bus_clk, it should be csb_clk
  Patch by Dave Liu, 21 July 2006


diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index ad6b3f6..bc689c1 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -333,7 +333,7 @@ #endif /* (CFG_HRCW_HIGH | RCWH_PCIHOST)
        gd->pci_clk    = pci_sync_in;

        gd->cpu_clk = gd->core_clk;
-       gd->bus_clk = gd->lbiu_clk;
+       gd->bus_clk = gd->csb_clk;
        return 0;
 }

[U-Boot-Users] Invalid MPC8349EMDS OR0 setting?

[David Hawkins]

Hey Dave,

While looking through the U-Boot source for the
MPC8349E-MDS board, I noticed the following:

u-boot/include/configs/MPC8349EMDS.h

CFG_OR0_PRELIM 0xFF806FF7

The '6' in the middle of this word corresponds
to bits 17 and 18, but in the reference manual
these bits are marked as reserved, and at processor
reset are 00b.

Since you and Ben have been working on this
board a while, I was wondering if there was
anything special about these particular bits,
eg. needed in silicon 1.0, but not the 1.1
on the MDS board.

Is this something I should try setting to 0,
test on the MDS board, and then submit a patch
for?

Also, do you know if the 2.0 silicon can
be dropped into the MDS board without change?

Thanks!
Dave

[U-Boot-Users] Invalid MPC8349EMDS OR0 setting?

[Liu Dave-r63238]

> 
> Hey Dave,
> 
> While looking through the U-Boot source for the
> MPC8349E-MDS board, I noticed the following:
> 
> u-boot/include/configs/MPC8349EMDS.h
> 
> CFG_OR0_PRELIM 0xFF806FF7
> 
> The '6' in the middle of this word corresponds
> to bits 17 and 18, but in the reference manual
> these bits are marked as reserved, and at processor
> reset are 00b.

Please refer to the latest reference manual about the two bits.
The bit 17 and 18 should be XAM. See the section 10.3.1.2.1
> 
> Since you and Ben have been working on this
> board a while, I was wondering if there was
> anything special about these particular bits,
> eg. needed in silicon 1.0, but not the 1.1
> on the MDS board.
> 
> Is this something I should try setting to 0,
> test on the MDS board, and then submit a patch
> for?
> 
> Also, do you know if the 2.0 silicon can
> be dropped into the MDS board without change?
> 
I don't recommend you put the 2.0 silicon to orginal MDS board.
Please contact with Freescale FAE or sales to get more information
about it.

-Dave

[U-Boot-Users] Invalid MPC8349EMDS OR0 setting?

[Liu Dave-r63238]

Please refer to the latest reference manual about the two bits. 
The bit 17 and 18 should be XAM. See the section 10.3.1.2.1

I don't recommend you put the 2.0 silicon to orginal MDS board directly.
Please contact with Freescale FAE or sales to get more information about
it.

> 
> Hey Dave,
> 
> While looking through the U-Boot source for the
> MPC8349E-MDS board, I noticed the following:
> 
> u-boot/include/configs/MPC8349EMDS.h
> 
> CFG_OR0_PRELIM 0xFF806FF7
> 
> The '6' in the middle of this word corresponds
> to bits 17 and 18, but in the reference manual
> these bits are marked as reserved, and at processor
> reset are 00b.
> 
> Since you and Ben have been working on this
> board a while, I was wondering if there was
> anything special about these particular bits,
> eg. needed in silicon 1.0, but not the 1.1
> on the MDS board.
> 
> Is this something I should try setting to 0,
> test on the MDS board, and then submit a patch
> for?
> 
> Also, do you know if the 2.0 silicon can
> be dropped into the MDS board without change?
> 

[U-Boot-Users] Invalid MPC8349EMDS OR0 setting?

[David Hawkins]

Hi Dave,

> Please refer to the latest reference manual about the two bits. 
> The bit 17 and 18 should be XAM. See the section 10.3.1.2.1

Yikes, thats subtle. The OR tables for GPCM lists those bits
as reserved, and reset and U-Boot is using the GPCM to access
flash ... so I would have interpreted 'Figure 10-3 Option
Registers (ORn) in GPCM' to mean those bits were reserved.

Thanks for the heads-up.

> I don't recommend you put the 2.0 silicon to orginal MDS board directly.
> Please contact with Freescale FAE or sales to get more information about
> it.

Ok, I will thanks.

Dave

[U-Boot-Users] Invalid MPC8349EMDS OR0 setting?

[Ben Warren]

Hi Dave,

I just used this blindly...  The boot flash is the only peripheral on CS0 and I certainly haven't seen any problems here, but it's probably best to follow the manual.

FYI - Don't hold your breath for rev2.0 silicon.  My understanding is that the next release will be early 2007 with rev3.0 silicon (renamed rev A).  Check with your rep... The next rev is supposed to be pin compatible, but with additional pins being used for more chip selects and DDR2 support.  If we have to spin our board I'm going to be royally pissed!

B-)
David Hawkins <dwh@ovro.caltech.edu> wrote: 
Hey Dave,

While looking through the U-Boot source for the
MPC8349E-MDS board, I noticed the following:

u-boot/include/configs/MPC8349EMDS.h

CFG_OR0_PRELIM 0xFF806FF7

The '6' in the middle of this word corresponds
to bits 17 and 18, but in the reference manual
these bits are marked as reserved, and at processor
reset are 00b.

Since you and Ben have been working on this
board a while, I was wondering if there was
anything special about these particular bits,
eg. needed in silicon 1.0, but not the 1.1
on the MDS board.

Is this something I should try setting to 0,
test on the MDS board, and then submit a patch
for?

Also, do you know if the 2.0 silicon can
be dropped into the MDS board without change?

Thanks!
Dave


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[U-Boot-Users] Invalid MPC8349EMDS OR0 setting?

[David Hawkins]

Hi Ben,

> I just used this blindly...  The boot flash is the only peripheral on 
> CS0 and I certainly haven't seen any problems here, but it's probably 
> best to follow the manual.

Yeah, but if you look at Dave's response, the section of the manual
Dave referred to does indeed reference those bits as XAM, but then
the GPCM OR table (and the other OR tables) refer to those bits as
reserved! Not exactly crystal clear.

> FYI - Don't hold your breath for rev2.0 silicon.  My understanding is 
> that the next release will be early 2007 with rev3.0 silicon (renamed 
> rev A).  Check with your rep... The next rev is supposed to be pin 
> compatible, but with additional pins being used for more chip selects 
> and DDR2 support.  If we have to spin our board I'm going to be royally 
> pissed!

Ohhh ... I've sent a request to my board subcontractor to start
talking to FAEs.

I'll be building prototypes in Nov/Dec. However, I had wanted to
use the Rev 2.0 silicon since it enables DDR2 and fixes the
external DMA errata (DMA_REQ/ACK/DONE not implemented).
Strangely though the errata rev 9 on the web site has
removed this errata listing (it was present in the rev 8
errata), and have even removed mention of the silicon 2.0.
Of course they might have just renamed the silicon 2.0
to MPC8349EA, but then there is no errata for that
silicon. Even more confusing is that the part numbering
scheme PDF lists parts ending in A as being silicon 3.0!

http://www.freescale.com/files/netcomm/doc/prod_num_scheme/MPC834XEFAMPNS.pdf

What silicon were you able to get for your boards?

Cheers
Dave