* [U-Boot-Users] MPC5840 local bus speed
2006-06-27 14:43 [U-Boot-Users] MPC5840 local bus speed Gerrit Van de Velde
@ 2006-10-02 15:08 ` Clemens Koller
0 siblings, 0 replies; 2+ messages in thread
From: Clemens Koller @ 2006-10-02 15:08 UTC (permalink / raw)
To: u-boot
Hi, Gerrit!
Gerrit Van de Velde wrote:
> Hi all,
>
> I'm not sure if it's entirely on topic but here we go:
> We've been trying to set the local bus speed of the MPC8540 to 82MHz
> without much success until now. We're using Uboot 1.1.4 with our own
> board.c code mostly ripped from the 8540ADS board.
> In the code there's some info about a workaround for the DLL of te cpu:
>
> /*
> * Errata LBC11.
> * Fix Local Bus clock glitch when DLL is enabled.
> *
> * If localbus freq is < 66Mhz, DLL bypass mode must be used.
> * If localbus freq is > 133Mhz, DLL can be safely enabled.
> * Between 66 and 133, the DLL is enabled with an override
> workaround.
> */
>
> But actually, the 82Mhz is in between those values. In this code, the
> U-Boot stops working after the LCRR is assigned and doesn't even get to
> the udelay part (checked with printfs)
>
> lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
> Udelay(200);
>
> Disabling or enabling has the same result, the clock speed of the bus
> has changed though to 82MHz (checked it with the scope).
>
> Has anyone of you some pointers on what to check or what to try out?
Hmm, not really. I didn't run into the LBC11 Errata yet.
I did some experiments with the LBC some time ago on 82MHz as well as on
166MHz when I did my UPM coding for the MPC8540 - no problems so far.
See some code snippets below, YMMV using U-Boot:
MPC8540 code examples to illustrate the Local Bus Clock setup from my
Linux 2.6.18 kernel module:
-----8<-----
/* 0. map the phys area to be able to write the UPM RAM patterns*/
ecam_map.virt = ioremap_nocache(ecam_map.phys, ecam_map.size);
/* speed up the local bus */
/* immap->im_lbc.lcrr=0x00010002; */ /* 166MHz fast */
immap->im_lbc.lcrr=0x00030004; /* 83MHz slow */
/* LCRR
* 0000 0000 0000 0001 0000 0000 0000 0010 0x00030004
* 0 DPY DLL bypass 0 DLL enabled
* 1 reserved 0
* 2-3 BUFCMDC 00. 4 (doesn't matter)
* 4-5 reserved 00
* 6-7 ECL Ext CAS latency 00. 4 (minimum)
* 8-13 reserved 0000.00
* 14-15 EADC ext addr delay 01. 1 cycle (minimum)
* 16-27 reserved 0000.0000.0000.
* 28-31 CLKDIV CCB to LBC 0010 div by 2
*/
/*local bus configuration register*/
immap->im_lbc.lbcr=0x00200000;
/* LBCR
* 0000 0000 0010 0000 0000 0000 0000 0000 0x00200000
* 0 LDIS local bus disable 0 enabled
* 1-7 reserved 000.0000.
* 8-9 BCTLC buf ctrl 00 W/#R control
* 10 AHD addr hold disable 1 highspeed
* 11-13 reserved 0.00
* 14 LPBSE parity 0 disabled
* 15 EPAR parity 0. odd
* 16-23 BMT bus monitor timing 0000.0000 default
* 24-31 reserved 0000
*/
/* 1. set up BRn and ORn registers */
/* set up BR4 and OR4 registers for 64k command io window */
immap->im_lbc.br4 = 0x00000000; /* clear br before touching or */
immap->im_lbc.or4 = (0x00000000-ECAM_FPGACMDSIZE)+0x6100; /*no bursts*/
//immap->im_lbc.or4 = 0xffff6100; /* 64kb, no bursts */
/* 1111 1111 1111 1111 0000 0001 0000 0000 */
immap->im_lbc.br4 = ECAM_FPGACMD+0x1881; /*ps=32bit, UPMA, set base and valid */
//immap->im_lbc.br4 = 0xfc101881; /* @fc01, PS=32bit, UPMA, set base and valid */
/* 1111 1100 0000 0000 0001 1000 1000 0001 */
/* set up CR5 and OR5 registers for 64k data io window */
/* clear valid bit, otherwise ORx is not programmable!!! */
immap->im_lbc.br5=0x00000000;
#if BURST
immap->im_lbc.or5 = (0x00000000-ECAM_FPGADATASIZE)+0x6000; /*bursts*/
//immap->im_lbc.or5 = 0xfff06000; /* 1MByte, bursts */
DBG("Bursts enabled!\n");
#else
immap->im_lbc.or5 = (0x00000000-ECAM_FPGADATASIZE)+0x6100; /*bursts inhibited*/
//immap->im_lbc.or5 = 0xfff06100; /* 1MByte, bursts inhibited */
DBG("Bursts disabled!\n");
#endif
/* default: 0xff006f67 */
/* OR5
* 1111 1111 0000 0000 0110 0000 0000 0111 0xff006816
* 00-16 AM address mask 0xff00.0 16 MBytes
* 17-18 reserved?? 11 manual unclear!
* 19 BCTLD buf ctrl disable 0. enabled
* 20-22 reserved 000
* 23 BI burst inhibit 0. bursts allowed
* 24-28 reserved 0000.0
* 29 TRLX timing relaxed 0 relax
* 30 EHTR ext. hold time 0 extend
* 31 EAD ext AL delay 0 delayes
*/
immap->im_lbc.br5 = ECAM_FPGADATA+0x1881; /* PS=32bit, UPMA, set base and valid */
//immap->im_lbc.br5=0xfc001881; /* @fc00, PS=32bit, UPMA, set base and valid */
/* BR5
* 1111 1100 0000 0000 0001 1000 1000 0001 0xfc001801
* 00-16 BA base address 0xfc00.0
* 17-18 reserved 00
* 19-20 PS port size 1.1 32bit
* 21-22 DECC error checking 00 disabled
* 23 WP Write Protect 0. r/w
* 24-26 MSEL Machine Select 100 UPMA
* 27 reserved 0.
* 28-29 ATOM 00 no atomic oprtations
* 30 reserved 0
* 31 V valid 1 valid
*/
-----8<-----
Good luck!
Clemens Koller
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