[U-Boot-Users] Where does U-Boot's CFI driver check for top/bottom boot?

[Tolunay Orkun <listmember@orkun.us>]

(Resending as original mail bounced by mail list)

Timur Tabi wrote:
> Can someone point me to the code where the CFI driver checks if the flash is 
> top-boot or bottom boot?  The spec says that that information is in offset 1E 
> of the Primary Vendor-Specific Extension Query Table, but I don't see any code 
> that references that.  Do I need to add an entry into flash.h for my part 
> (29LV640BT)?
> 

The code that you should be looking is flash_get_size(). Take a look at
the section of code that reads 4 bytes at (FLASH_OFFSET_ERASE_REGIONS +
i * 4) and after a computation sets erase_region_size. If you enable
DEBUG in U-Boot you should see the debug output there which prints the
size of each erase region. Can you do make clean and #define DEBUG and
rebuilt and reflash debug build of u-boot. This should enable those
debug output.

The current CFI driver is checking vendor specific extension query
table. It is only working with standard CFI tables. Vendor specific
tables can vary greatly from manufacturer to manufacturer and even from
model to model for the same manufacturer. This table is not easily
usable. I personally wouldn't want to add code looking to vendor
specific tables unless there is no other means that we can find this
information from the primary tables. For example, the top/bottom boot
code is not available on Intel vendor specific table for
top/bottom/uniform boot sector parts.

I just looked at the datasheet of your flash part as well as datasheet
of a couple of intel flash parts as well as the current code. As I
suspected for your particular part, it looks like they are using the
same values for "Erase Bank Area 1" and "Erase Bank Area 2" irrespective
of top boot or bottom boot flash. I think, this is fundamentally wrong
and non-compliant with the general CFI standard.

I will look at some AMD part datasheets. If this is generally available
on all AMD and AMD like parts, we can add it as a patch for AMD only.
Otherwise, we will either add CONFIG_GEOMETRY_REVERSED definition or
restrict a patch to specific vendor ids (and possibly part ids) which is
then a pain to manage.

Best regards,
Tolunay