From mboxrd@z Thu Jan  1 00:00:00 1970
From: Timur Tabi <timur@freescale.com>
Date: Mon, 06 Nov 2006 16:00:12 -0600
Subject: [U-Boot-Users] Where does U-Boot's CFI driver check for
 top/bottom boot?
In-Reply-To: <454D7BF3.2000400@orkun.us>
References: <454B6B23.1060702@freescale.com> <454D7BF3.2000400@orkun.us>
Message-ID: <454FB06C.2080404@freescale.com>
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To: u-boot@lists.denx.de

Tolunay Orkun wrote:

> I just looked at the datasheet of your flash part as well as datasheet
> of a couple of intel flash parts as well as the current code. As I
> suspected for your particular part, it looks like they are using the
> same values for "Erase Bank Area 1" and "Erase Bank Area 2" irrespective
> of top boot or bottom boot flash. I think, this is fundamentally wrong
> and non-compliant with the general CFI standard.

Using the PDF you specified, I see that my chip has a value of 03h for the 
"Top/Bottom Boot Sector Flag", at offset (P+F)h.  That indicates a top-boot, 
which is correct (smaller sectors at the end of memory).

Why can't we just check this byte if we're on an AMD part, and adjust accordingly?

-- 
Timur Tabi
Linux Kernel Developer @ Freescale