[U-Boot-Users] Altera Stratix II support

[U-Boot-Users] Altera Stratix II support

[eran liberty]

Hi All,

I am already knee deep in adding Altera Stratix II support to the
u-boot via the fpga command (currently xlinix & acex1k are
supported)...

of course I will re-post when i am done.

My only question is,

Am i reinventing the wheel?
Is it already implemented anywhere?

If i am, where can I find a reference to the work already done?

If not I will soon give you one :)

Liberty

[U-Boot-Users] Altera Stratix II support

[David Hawkins]

Hi Liberty,

> I am already knee deep in adding Altera Stratix II support to the
> u-boot via the fpga command (currently xlinix & acex1k are
> supported)...
> 
> of course I will re-post when i am done.
> 
> My only question is,
> 
> Am i reinventing the wheel?
> Is it already implemented anywhere?
> 
> If i am, where can I find a reference to the work already done?
> 
> If not I will soon give you one :)

I haven't looked for it yet, but I plan to add support
too eventually (= months from now when I get boards).

I haven't looked at the code, but here's how I plan to
configure my FPGAs. Your method may be different, so
perhaps between us we can come up with a consistent API.

The board I am designing will contain an MPC8349E, and
Altera Stratix II system controller FPGA on the processor
local bus, and then 4 other programmable FPGAs. A
board placement PDF is here;

http://www.ovro.caltech.edu/~dwh/carma_board/carma_board_placement.pdf

and engineering documents are here

http://www.ovro.caltech.edu/~dwh/carma_board/

The system controller FPGA will boot from Flash, a MAX II
CPLD will configure it on power-up, and then it'll bring the
PPC out of reset, which will then boot through Flash located
off the system controller FPGA (hence the system controller
comes to life before the processor). The other four FPGAs
will be programmed as the application dictates.

So given U-Boot running, I'd imagine tftp'ing RBF
(raw binary format) files generated by Quartus over to the
board. I'd then copy the files to a block of memory which
maps in my system controller to a fast-passive-parallel (FPP)
programmer. That state machine then programs the FPGAs.
In Linux the same procedure would be hidden behind
a driver so I could dd the RBFs into /dev/fgpa_fpp or
/sys/.../firmware.

The point of mapping the FPP programmer into a block of
local bus memory addresses is so that I can use the MPC8349E
DMA controller to DMA the RBF files from SDRAM memory to the
programmer memory (eg. from files in a RAM filesystem).
According to the datasheet MPC8349E DMA controller won't
burst with a fixed destination address (FIFO mode), so I'll
just fake it out and let it DMA to what it thinks
is an incrementing address location.

How are you planning on programming your FPGA?

Cheers
Dave

[U-Boot-Users] Altera Stratix II support

[eran liberty]

Hi Dave (and all),

Well its you lucky day,

By the time I you will need it I will already be done with it and you
will have it.

I am using the a custom board with a MPC8548 as its main processor..
so you should be able to convert it to your use with real ease.

the strategy, software wise, is:
1. not touch fpga.c /fpga.h
2. Add the needed enums to altera.h / switch cases to altera.c
3. Add an StratixII.c / StratixII.h general purpose driver
4. Add a vendor specific /board/{VENDOR}}/yourname_fpga.c that contain
the board specific function (like enabling gpio and stuff, raise the
whatshellwecallit bit, ect. )

hardware wise:
we do not have TSEC2 on our board... so by setting the right bits we
can its legs as gpio...

once its ready I will post a patch (against 1.1.6 stable) and will
ready to help if there are any problems.


On 5/18/07, David Hawkins <dwh@ovro.caltech.edu> wrote:
> Hi Liberty,
>
> > I am already knee deep in adding Altera Stratix II support to the
> > u-boot via the fpga command (currently xlinix & acex1k are
> > supported)...
> >
> > of course I will re-post when i am done.
> >
> > My only question is,
> >
> > Am i reinventing the wheel?
> > Is it already implemented anywhere?
> >
> > If i am, where can I find a reference to the work already done?
> >
> > If not I will soon give you one :)
>
> I haven't looked for it yet, but I plan to add support
> too eventually (= months from now when I get boards).
>
> I haven't looked at the code, but here's how I plan to
> configure my FPGAs. Your method may be different, so
> perhaps between us we can come up with a consistent API.
>

any changes between our boards will be placed in the
board specific file, so no worries there.

> The board I am designing will contain an MPC8349E, and
> Altera Stratix II system controller FPGA on the processor
> local bus, and then 4 other programmable FPGAs. A
> board placement PDF is here;

I have a 3 FPGA on the local bus system so its pretty close.

>
> http://www.ovro.caltech.edu/~dwh/carma_board/carma_board_placement.pdf
>
> and engineering documents are here
>
> http://www.ovro.caltech.edu/~dwh/carma_board/
>
> The system controller FPGA will boot from Flash, a MAX II
> CPLD will configure it on power-up, and then it'll bring the
> PPC out of reset, which will then boot through Flash located
> off the system controller FPGA (hence the system controller
> comes to life before the processor). The other four FPGAs
> will be programmed as the application dictates.
>

I am going to cut expanses on the CPLD (have it now but intend to
solder it out). So the Uboot will reset the FPGA and than program it.

> So given U-Boot running, I'd imagine tftp'ing RBF
> (raw binary format) files generated by Quartus over to the
> board. I'd then copy the files to a block of memory which
> maps in my system controller to a fast-passive-parallel (FPP)
> programmer. That state machine then programs the FPGAs.
> In Linux the same procedure would be hidden behind
> a driver so I could dd the RBFs into /dev/fgpa_fpp or
> /sys/.../firmware.
>

I am going to add the Fast Passive Parallel loading style, so again
you have a tight fit here.

> The point of mapping the FPP programmer into a block of
> local bus memory addresses is so that I can use the MPC8349E
> DMA controller to DMA the RBF files from SDRAM memory to the
> programmer memory (eg. from files in a RAM filesystem).
> According to the datasheet MPC8349E DMA controller won't
> burst with a fixed destination address (FIFO mode), so I'll
> just fake it out and let it DMA to what it thinks
> is an incrementing address location.

Here we are differ... I intend to do it as simple as possible. This is
a rare operation, done only once on start up event. If your up time is
so crucial go ahead and DMA it. I can spare the extra 3 sec on
directly putting the stuff on the bus.

>
> How are you planning on programming your FPGA?
>
> Cheers
> Dave
>

Having said all that... I am still not too proud to stop right now and
take someone elses already made job, if anyone will show me it.
again, Is There already an implementation for Altera Startix II out
there hidden from me?

Liberty

[U-Boot-Users] Altera Stratix II support

[David Hawkins]

eran liberty wrote:
> Hi Dave (and all),
> 
> Well its you lucky day,
> 
> By the time I you will need it I will already be done with it and you
> will have it.
> 

Great!

Dave

[U-Boot-Users] Altera Stratix II support

[eran liberty]

Hi David & All,

I have successfully integrated Altera Stratix II (fast passive
parallel) into the existing FPGA framework within u-boot.

so in u-boot it looks like this

==================== u-boot console =====================================
=> fpga info
Altera Device
Descriptor @ 0x0fff474c
Family:         Stratix II
Interface type: Fast Passive Parallel (FPP)
Device Size:    1 bytes
Cookie:         0x0 (0)
Device Function Table @ 0x0fff255c
=> bunzip ff000000 200000 3c58c
BUNZIP2: decompressed image address & size: 0x00200000 0x930d2c (9637164)
=> fpga load 0 200000 930d2c
loading to fpga  done.
=========================================================================

I have attached two patches which are applied against the latest
stable u-boot-1.1.6.
The first is only the generic stuff needed for Stratix II support.
The second contains my new board with a specific implementation of a
Stratix II FPGA along with other add-ons and fixes

If there is any wish / demand / need to port any or all of this into
the main trunk, tell me what to be done as I have never done so in the
past.

here is a summery of what can be found in the patches:

u-boot-stratixII.patch : the basic generic part for Stratix II
/common/altera.c : Added Altera_StratixII case
/include/altera.h : Added Macros and Enums to support Stratix II
/common/stratixII.c : New file that implements Stratix II based on ACEX1K.c
/include/stratixII.h : New file Stratix II header
/common/Makefile : Added "stratixII.o"
/common/fpga.c : Added "const" to suppress warning
/include/common.h : Added ndelay() declaration
/include/exports.h : Added ndelay() export
/lib_ppc/time.c : Added ndelay() implementation

u-boot-exsw6000.patch: contains everything in u-boot-stratixII.patch plus
/board/extricom/exsw6000/config.mk : new
/board/extricom/exsw6000/exsw6000.c : new
/board/extricom/exsw6000/exsw6000_fpga.c : New board specific Stratix
II implementation
/board/extricom/exsw6000/exsw6000_fpga.h : New board specific Stratix II header
/board/extricom/exsw6000/ft_board.c : new
/board/extricom/exsw6000/init.S : new
/board/extricom/exsw6000/Makefile : new
/board/extricom/exsw6000/u-boot.lds : new
/include/configs/EXSW6000.h : new
/Makefile : added EXSW6000_config target
/common/cmd_misc.c : Added bunzip2 command depends on CONFIG_BZIP2 macro defined
/cpu/mpc85xx/cpu.c: added reset by using rstcr register depands on
CONFIG_RESET_RSCTR or CONFIG_RESET_DBCR0 macro defined. The copyrights
for this are not mine. I have taken it from somewhere on the net! alas
I cant remember from where. :(
/include/asm-ppc/immap_85xx.h: added the rstcr register in the memory map

/drivers/cfi_flash.c : added security check to prevent flash function
to buffer overrun when Flash size as read from the hardware does not
match the flash size define by the config file. Also added
CONFIG_FORCE_FLASH_BANK_SIZE that can be used to set the Config size
over the read / calculated one.

Have fun,

The forum bot admin wont let me attach my patches so i put them on
yousend it... if the credits run out on some1 let me know...

u-boot-statixII.patch
http://download.yousendit.com/91048F0F125DDD5E

u-boot-exsw6000.patch
http://download.yousendit.com/44C713D149624E03

[U-Boot-Users] Altera Stratix II support

[Wolfgang Denk]

In message <ffc2b1d40705311610j405896f7yeb9b89268d9477de@mail.gmail.com> you wrote:
> 
> I have attached two patches which are applied against the latest
> stable u-boot-1.1.6.

U-Boot 1.1.6 is by far not "latest". Actually  it  is  very  old  and
outdated.  Please resubmit your patches against *current* code, i. e.
against the top-of-tree version in the git repository.

Your patches cannot be applied current code:

-> patch -p1 --dry-run </tmp/patch1
patching file common/altera.c
Hunk #4 FAILED at 60.
Hunk #5 succeeded at 99 (offset 5 lines).
Hunk #6 succeeded at 218 with fuzz 2 (offset 90 lines).
Hunk #7 FAILED at 243.
Hunk #8 FAILED at 263.
Hunk #9 FAILED at 306.
Hunk #10 succeeded at 164 (offset -71 lines).
4 out of 10 hunks FAILED -- saving rejects to file common/altera.c.rej
patching file common/fpga.c
patching file common/Makefile
Hunk #1 FAILED at 27.
1 out of 1 hunk FAILED -- saving rejects to file common/Makefile.rej
patching file common/stratixII.c
patching file include/altera.h
Hunk #1 FAILED at 27.
Hunk #2 FAILED at 49.
Hunk #3 succeeded at 92 (offset 4 lines).
2 out of 3 hunks FAILED -- saving rejects to file include/altera.h.rej
patching file include/common.h
Hunk #1 succeeded at 559 (offset 8 lines).
patching file include/exports.h
patching file include/stratixII.h
patching file lib_ppc/time.c


Also, please clean up all your  many  coding  style  violations  (see
http://www.denx.de/wiki/UBoot/CodingStyle):   trailing  white  space,
indentation not by TABs, too long lines, indentation not by multiples
of 8 characters, missing space after function names, bad brace  style
(board/extricom/exsw6000/exsw6000_fpga.c), etc.

Also, please make sure to keep lists (like of objects) alphabetically
sorted (common/Makefile etc.).

Also, make sure that "make clean" removes all files and directories
you create during your build ($(obj)../../cds/common ?).


Finally, please break up your monster patches into smaller,  indepen-
dent   chunks.   For   example,   adding   the  "bunzip"  command  to
common/cmd_misc.c is unrelated to the rest of your patches  and  must
be  submitted  as  a  separate  patch.  Ditto  for  your  changes  to
drivers/cfi_flash.c and other similar things.

Thanks.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
"In the long run, every program becomes rococo, and then rubble."
- Alan Perlis

[U-Boot-Users] Altera Stratix II support

[eran liberty]

>
> Finally, please break up your monster patches into smaller,  indepen-
> dent   chunks.   For   example,   adding   the  "bunzip"  command  to
> common/cmd_misc.c is unrelated to the rest of your patches  and  must
> be  submitted  as  a  separate  patch.  Ditto  for  your  changes  to
> drivers/cfi_flash.c and other similar things.
>
> Thanks.
>
> Best regards,
>
> Wolfgang Denk
>

done.

the followong pathces are applied against the latest snapshot...

[U-Boot-Users] Altera Stratix II support

[eran liberty]

Altera Stratix II support (generic implemetation)
===================start of patch =============================
diff -x .svn -Nuar u-boot.git/common/altera.c u-boot-exsw6000/common/altera.c
--- u-boot.git/common/altera.c	2007-05-28 02:11:11.000000000 +0300
+++ u-boot-exsw6000/common/altera.c	2007-06-03 22:15:48.000000000 +0300
@@ -1,4 +1,7 @@
 /*
+ * (C) Copyright 2007
+ * Eran Liberty, Extricom , eran.liberty at gmail.com
+ *
  * (C) Copyright 2003
  * Steven Scholz, imc Measurement & Control, steven.scholz at imc-berlin.de
  *
@@ -30,6 +33,7 @@
  */
 #include <common.h>
 #include <ACEX1K.h>
+#include <stratixII.h>

 /* Define FPGA_DEBUG to get debug printf's */
 /* #define FPGA_DEBUG */
@@ -43,7 +47,7 @@
 #if (CONFIG_FPGA & CFG_FPGA_ALTERA)

 /* Local Static Functions */
-static int altera_validate (Altera_desc * desc, char *fn);
+static int altera_validate (Altera_desc * desc,const char *fn);

 /* ------------------------------------------------------------------------- */
 int altera_load( Altera_desc *desc, void *buf, size_t bsize )
@@ -69,6 +73,16 @@
 					__FUNCTION__);
 #endif
 			break;
+		case Altera_StratixII:
+#if (CONFIG_FPGA & CFG_STRATIX_II)
+			PRINTF ("%s: Launching the Stratix II Loader...\n",
+				   __FUNCTION__);
+			ret_val = StratixII_load (desc, buf, bsize);
+#else
+			printf ("%s: No support for Stratix II devices.\n",
+				   __FUNCTION__);
+#endif
+			break;

 		default:
 			printf ("%s: Unsupported family type, %d\n",
@@ -97,6 +111,16 @@
 					__FUNCTION__);
 #endif
 			break;
+		case Altera_StratixII:
+#if (CONFIG_FPGA & CFG_STRATIX_II)
+			PRINTF ("%s: Launching the Stratix II Reader...\n",	
+				   __FUNCTION__);
+			ret_val = StratixII_dump (desc, buf, bsize);
+#else
+			printf ("%s: No support for Stratix II devices.\n",	
+				   __FUNCTION__);
+#endif
+			break;

 		default:
 			printf ("%s: Unsupported family type, %d\n",
@@ -117,6 +141,9 @@
 		case Altera_ACEX1K:
 			printf ("ACEX1K\n");
 			break;
+		case Altera_StratixII:
+			printf ("Stratix II\n");
+			break;
 			/* Add new family types here */
 		case Altera_CYC2:
 			printf ("CYCLON II\n");
@@ -142,6 +169,9 @@
 		case altera_jtag_mode:		/* Not used */
 			printf ("JTAG Mode\n");
 			break;
+		case fast_passive_parallel:
+			printf ("Fast Passive Parallel (FPP)\n");
+			break;
 			/* Add new interface types here */
 		default:
 			printf ("Unsupported interface type, %d\n", desc->iface);
@@ -166,6 +196,14 @@
 						__FUNCTION__);
 #endif
 				break;
+			case Altera_StratixII:
+#if (CONFIG_FPGA & CFG_STRATIX_II)
+				StratixII_info (desc);
+#else
+				printf ("%s: No support for Stratix II  devices.\n",
+					   __FUNCTION__);
+#endif	
+				break;
 				/* Add new family types here */
 			default:
 				/* we don't need a message here - we give one up above */
@@ -199,6 +237,16 @@
 					__FUNCTION__);
 #endif
 			break;
+
+		case Altera_StratixII:
+#if (CONFIG_FPGA & CFG_STRATIX_II)
+			ret_val = StratixII_reloc (desc, reloc_offset);
+#else
+			printf ("%s: No support for Stratix II devices.\n",
+				   __FUNCTION__);
+#endif	
+			break;
+
 		case Altera_CYC2:
 #if (CONFIG_FPGA & CFG_CYCLON2)
 			ret_val = CYC2_reloc (desc, reloc_offset);
@@ -219,7 +267,7 @@

 /* ------------------------------------------------------------------------- */

-static int altera_validate (Altera_desc * desc, char *fn)
+static int altera_validate (Altera_desc * desc, const char *fn)
 {
 	int ret_val = FALSE;

diff -x .svn -Nuar u-boot.git/common/Makefile u-boot-exsw6000/common/Makefile
--- u-boot.git/common/Makefile	2007-05-28 02:11:11.000000000 +0300
+++ u-boot-exsw6000/common/Makefile	2007-06-03 22:23:57.000000000 +0300
@@ -27,8 +27,9 @@

 AOBJS	=

-COBJS	= main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
+COBJS	= main.o ACEX1K.o altera.o stratixII.o \
+	  bedbug.o circbuf.o cmd_autoscript.o \
 	  cmd_bdinfo.o cmd_bedbug.o cmd_bmp.o cmd_boot.o cmd_bootm.o \
 	  cmd_cache.o cmd_console.o \
 	  cmd_date.o cmd_dcr.o cmd_diag.o cmd_display.o cmd_doc.o cmd_dtt.o \
diff -x .svn -Nuar u-boot.git/common/stratixII.c
u-boot-exsw6000/common/stratixII.c
--- u-boot.git/common/stratixII.c	1970-01-01 02:00:00.000000000 +0200
+++ u-boot-exsw6000/common/stratixII.c	2007-06-03 21:55:51.000000000 +0300
@@ -0,0 +1,186 @@
+/*
+ * (C) Copyright 2007
+ * Eran Liberty, Extricom , eran.liberty at gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>		/* core U-Boot definitions */
+#include <altera.h>
+
+#if (CONFIG_FPGA & (CFG_ALTERA | CFG_STRATIX_II))
+
+int StratixII_fpp_load(Altera_desc * desc, void *buf, size_t bsize);
+int StratixII_fpp_dump(Altera_desc * desc, void *buf, size_t bsize);
+
+/****************************************************************/
+/* Stratix II Generic Implementation                            */
+int StratixII_load (Altera_desc * desc, void *buf, size_t bsize)
+{
+	int ret_val = FPGA_FAIL;
+
+	switch (desc->iface) {
+	case fast_passive_parallel:
+		ret_val = StratixII_fpp_load(desc, buf, bsize);
+		break;
+
+		/* Add new interface types here */
+	default:
+		printf ("%s: Unsupported interface type, %d\n", __FUNCTION__, desc->iface);
+	}
+	return ret_val;
+}
+
+int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize)
+{
+	int ret_val = FPGA_FAIL;
+
+	switch (desc->iface) {
+	case fast_passive_parallel:
+		ret_val = StratixII_fpp_dump(desc, buf, bsize);
+		break;
+		/* Add new interface types here */
+	default:
+		printf ("%s: Unsupported interface type, %d\n", __FUNCTION__, desc->iface);
+	}
+	return ret_val;
+}
+
+int StratixII_info( Altera_desc *desc )
+{
+	return FPGA_SUCCESS;
+}
+
+int StratixII_reloc (Altera_desc * desc, ulong reloc_offset)
+{
+	int i;
+	void** func_table;
+
+	desc->iface_fns = (void*)((ulong)(desc->iface_fns) + reloc_offset);
+	for (i=0,func_table = (void**)desc->iface_fns;i<
sizeof(altera_board_specific_func)/sizeof(void*);i++) {
+		func_table[i] = (void*)((ulong)(func_table[i]) + reloc_offset);
+	}
+	return FPGA_SUCCESS;
+}
+
+#endif
+
+/************************************************************/
+/* Stratix II Fast Passive Parallel  Generic Implementation */
+int StratixII_fpp_dump(Altera_desc * desc, void *buf, size_t bsize)
+{
+	printf("Stratix II Fast Passive Parallel dump is not implemented\n");
+	return FPGA_FAIL;
+}
+
+int StratixII_fpp_load(Altera_desc * desc, void *buf, size_t bsize)
+{
+	altera_board_specific_func *fns;
+	int cookie;
+	int ret_val = FPGA_FAIL;
+	int bytecount;
+	char *buff = buf;
+
+	if (!desc) {
+		printf("%s(%d) Altera_desc missing\n",__FUNCTION__,__LINE__);
+		return FPGA_FAIL;
+	}
+	if (!buff) {
+		printf("%s(%d) buffer is missing\n",__FUNCTION__,__LINE__);
+		return FPGA_FAIL;
+	}
+	if (!bsize) {
+		printf("%s(%d) size is zero\n",__FUNCTION__,__LINE__);
+		return FPGA_FAIL;
+	}
+	if (!desc->iface_fns) {
+		printf("%s(%d) Altera_desc function interface table is
missing\n",__FUNCTION__,__LINE__);
+		return FPGA_FAIL;
+	}
+	fns = (altera_board_specific_func *)(desc->iface_fns);
+	cookie = desc->cookie;
+
+	if (!(fns->config && fns->status && fns->done && fns->data && fns->abort)) {
+		printf("%s(%d) Missing some function in the function interface
table\n",__FUNCTION__,__LINE__);
+		return FPGA_FAIL;
+	}
+
+	/* 1. give board specific a chance to do anything before we start */
+	if (fns->pre) {
+		if ((ret_val = fns->pre(cookie)) < 0 ) {
+			return ret_val;
+		}
+	}
+
+	/* from this point on we must fail gracfully by calling lower layer abort */
+
+	/* 2. Strat burn cycle by deasserting config for t_CFG and waiting
t_CF2CK after reaserted*/
+	fns->config(0,1,cookie);
+	udelay(2); /* nCONFIG low pulse width 2usec*/
+	fns->config(1,1,cookie);
+	udelay(100); /* nCONFIG high to first rising edge on DCLK */
+
+	/* 3. Start the Data cycle with clk deasserted*/
+	bytecount = 0;
+	fns->clk(0,1,cookie);
+
+	printf("loading to fpga    ");
+	while(bytecount < bsize) {
+		/* 3.1 check stratix has not signaled us an error */
+		if (fns->status(cookie) != 1) {
+			printf("\n%s(%d) Stratix failed (byte transfered till failure
0x%x)\n",__FUNCTION__,__LINE__,bytecount);
+			fns->abort(cookie);
+			return FPGA_FAIL;
+		}
+		/* 3.2 put data on the bus */
+		fns->data(buff[bytecount++],1,cookie);
+		ndelay(5);
+		fns->clk(1,1,cookie);
+		ndelay(5);
+		fns->clk(0,1,cookie);
+
+		/* 3.3 while clk is deasserted it is safe to print some progress indication*/
+		if ((bytecount % (bsize / 100)) == 0) {
+			printf("\b\b\b%02d\%",bytecount*100/bsize);
+		}
+	}
+
+	/* 4. Set one last clock and check conf done signal */
+	fns->clk(1,1,cookie);
+	udelay(100);
+	if (!fns->done(cookie)) {
+		printf(" error!.\n");
+		fns->abort(cookie);
+		return FPGA_FAIL;
+	}
+	else {
+		printf("\b\b\b done.\n");
+	}
+
+	/* 5. call lower layer post configuration */
+	if (fns->post) {
+		if ((ret_val = fns->pre(cookie)) < 0 ) {
+			fns->abort(cookie);
+			return ret_val;
+		}
+	}
+
+	return FPGA_SUCCESS;
+}
diff -x .svn -Nuar u-boot.git/include/altera.h u-boot-exsw6000/include/altera.h
--- u-boot.git/include/altera.h	2007-05-28 02:11:11.000000000 +0300
+++ u-boot-exsw6000/include/altera.h	2007-06-03 22:13:42.000000000 +0300
@@ -27,22 +27,21 @@
 #ifndef _ALTERA_H_
 #define _ALTERA_H_

-/*
- * See include/xilinx.h for another working example.
- */
-
 /* Altera Model definitions
  *********************************************************************/
 #define CFG_ACEX1K		CFG_FPGA_DEV( 0x1 )
 #define CFG_CYCLON2		CFG_FPGA_DEV( 0x2 )
+#define CFG_STRATIX_II		CFG_FPGA_DEV( 0x4 )

 #define CFG_ALTERA_ACEX1K	(CFG_FPGA_ALTERA | CFG_ACEX1K)
 #define CFG_ALTERA_CYCLON2	(CFG_FPGA_ALTERA | CFG_CYCLON2)
+#define CFG_ALTERA_STRATIX_II	(CFG_FPGA_ALTERA | CFG_STRATIX_II)
 /* Add new models here */

 /* Altera Interface definitions
  *********************************************************************/
 #define CFG_ALTERA_IF_PS	CFG_FPGA_IF( 0x1 )	/* passive serial */
+#define CFG_ALTERA_IF_FPP	CFG_FPGA_IF( 0x2 )	/* fast passive parallel */
 /* Add new interfaces here */

 typedef enum {				/* typedef Altera_iface */
@@ -52,15 +51,17 @@
 	passive_parallel_asynchronous,	/* parallel data */
 	passive_serial_asynchronous,	/* serial data w/ internal clock (not used)	*/
 	altera_jtag_mode,		/* jtag/tap serial (not used ) */
+	fast_passive_parallel,          /* fast passive parallel (FPP) */
 	max_altera_iface_type		/* insert all new types before this */
 } Altera_iface;				/* end, typedef Altera_iface */

 typedef enum {			/* typedef Altera_Family */
-    min_altera_type,		/* insert all new types after this */
-    Altera_ACEX1K,		/* ACEX1K Family */
-    Altera_CYC2,		/* CYCLONII Family */
-/* Add new models here */
-    max_altera_type		/* insert all new types before this */
+	min_altera_type,		/* insert all new types after this */
+	Altera_ACEX1K,		/* ACEX1K Family */
+	Altera_CYC2,		/* CYCLONII Family */
+	Altera_StratixII,           /* StratixII Familiy */
+	/* Add new models here */
+	max_altera_type		/* insert all new types before this */
 } Altera_Family;		/* end, typedef Altera_Family */

 typedef struct {		/* typedef Altera_desc */
@@ -91,4 +92,15 @@
 typedef int (*Altera_abort_fn)( int cookie );
 typedef int (*Altera_post_fn)( int cookie );

+typedef struct {
+	Altera_pre_fn pre;
+	Altera_config_fn config;
+	Altera_status_fn status;
+	Altera_done_fn done;
+	Altera_clk_fn clk;
+	Altera_data_fn data;
+	Altera_abort_fn abort;
+	Altera_post_fn post;
+} altera_board_specific_func;
+
 #endif /* _ALTERA_H_ */
diff -x .svn -Nuar u-boot.git/include/common.h u-boot-exsw6000/include/common.h
--- u-boot.git/include/common.h	2007-05-28 02:11:11.000000000 +0300
+++ u-boot-exsw6000/include/common.h	2007-06-03 19:41:02.000000000 +0300
@@ -559,6 +559,7 @@

 /* lib_$(ARCH)/time.c */
 void	udelay	      (unsigned long);
+void	ndelay	      (unsigned long);
 ulong	usec2ticks    (unsigned long usec);
 ulong	ticks2usec    (unsigned long ticks);
 int	init_timebase (void);
diff -x .svn -Nuar u-boot.git/include/exports.h
u-boot-exsw6000/include/exports.h
--- u-boot.git/include/exports.h	2007-05-28 02:11:11.000000000 +0300
+++ u-boot-exsw6000/include/exports.h	2007-05-27 13:16:57.000000000 +0300
@@ -17,6 +17,7 @@
 void *malloc(size_t);
 void free(void*);
 void udelay(unsigned long);
+void ndelay(unsigned long);
 unsigned long get_timer(unsigned long);
 void vprintf(const char *, va_list);
 void do_reset (void);
diff -x .svn -Nuar u-boot.git/include/stratixII.h
u-boot-exsw6000/include/stratixII.h
--- u-boot.git/include/stratixII.h	1970-01-01 02:00:00.000000000 +0200
+++ u-boot-exsw6000/include/stratixII.h	2007-05-22 11:45:21.000000000 +0300
@@ -0,0 +1,33 @@
+/*
+ * (C) Copyright 2007
+ * Eran Liberty, Extricom, eran.liberty at gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#ifndef _STRATIXII_H_
+#define _STRATIXII_H_
+
+extern int StratixII_load( Altera_desc *desc, void *image, size_t size );
+extern int StratixII_dump( Altera_desc *desc, void *buf, size_t bsize );
+extern int StratixII_info( Altera_desc *desc );
+extern int StratixII_reloc( Altera_desc *desc, ulong reloc_off );
+
+#endif /* _STRATIXII_H_ */
+
diff -x .svn -Nuar u-boot.git/lib_ppc/time.c u-boot-exsw6000/lib_ppc/time.c
--- u-boot.git/lib_ppc/time.c	2007-05-28 02:11:11.000000000 +0300
+++ u-boot-exsw6000/lib_ppc/time.c	2007-06-03 22:03:21.000000000 +0300
@@ -60,6 +60,15 @@

 /* ------------------------------------------------------------------------- */

+void ndelay(unsigned long nsec)
+{
+	ulong ticks = usec2ticks(1)*nsec/1000 +1;
+	
+	wait_ticks (ticks);
+}
+
+/* ------------------------------------------------------------------------- */
+
 unsigned long ticks2usec(unsigned long ticks)
 {
 	ulong tbclk = get_tbclk();

=====================end of patch =======================

[U-Boot-Users] Altera Stratix II support

[eran liberty]

adds the reset register to 85xx immap
================ sof ===================
diff -x .svn -Nuar u-boot.git/include/asm-ppc/immap_85xx.h
u-boot-exsw6000/include/asm-ppc/immap_85xx.h
--- u-boot.git/include/asm-ppc/immap_85xx.h	2007-05-28 02:11:11.000000000 +0300
+++ u-boot-exsw6000/include/asm-ppc/immap_85xx.h	2007-05-29
10:13:11.000000000 +0300
@@ -1548,7 +1548,9 @@
 	char	res9[12];
 	uint	pvr;		/* 0xe00a0 - Processor version register */
 	uint	svr;		/* 0xe00a4 - System version register */
-	char	res10[3416];
+	char    res9a[8];
+	uint    rstcr;          /* 0xe00b0 - Reset control register */
+	char    res10[3404];
 	uint	clkocr;		/* 0xe0e00 - Clock out select register */
 	char	res11[12];
 	uint	ddrdllcr;	/* 0xe0e10 - DDR DLL control register */
================ eof ===================

[U-Boot-Users] Altera Stratix II support

[eran liberty]

adds the the sub command loadi to fpga.
this will load an fpga image that was u-boot packed with mkimage.
the image may be plain, gzip or bzip2 as with the kernel and fs images.
=============== sof =======================
diff -x .svn -Nuar u-boot.git/common/cmd_fpga.c
u-boot-exsw6000/common/cmd_fpga.c
--- u-boot.git/common/cmd_fpga.c	2007-05-28 02:11:11.000000000 +0300
+++ u-boot-exsw6000/common/cmd_fpga.c	2007-06-03 22:13:42.000000000 +0300
@@ -32,6 +32,7 @@
 #endif
 #include <fpga.h>
 #include <malloc.h>
+#include <bzlib.h>

 #if 0
 #define	FPGA_DEBUG
@@ -45,6 +46,8 @@

 #if defined (CONFIG_FPGA) && ( CONFIG_COMMANDS & CFG_CMD_FPGA )

+extern int gunzip(void *dst, int dstlen, unsigned char *src, unsigned
long *lenp);
+
 /* Local functions */
 static void fpga_usage (cmd_tbl_t * cmdtp);
 static int fpga_get_op (char *opstr);
@@ -56,6 +59,89 @@
 #define FPGA_LOADB  2
 #define FPGA_DUMP   3
 #define FPGA_LOADMK 4
+#define FPGA_LOADI  5
+
+/* Load an image */
+int fpga_loadi( int devnum, void *buf)
+{
+	ulong addr = (ulong)(buf);
+	ulong data, len, checksum;
+	image_header_t hdr;
+	unsigned int unc_len;
+	unsigned int *punc_len = &unc_len;
+	int i;
+	
+	/* Copy header so we can blank CRC field for re-calculation */
+#ifdef CONFIG_HAS_DATAFLASH
+	if (addr_dataflash(addr)){
+		read_dataflash(addr, sizeof(image_header_t), (char *)&hdr);
+	} else
+#endif
+		memmove (&hdr, (char *)addr, sizeof(image_header_t));
+	if (ntohl(hdr.ih_magic) != IH_MAGIC) {
+		puts ("Bad Magic Number\n");
+		return 1;
+	}
+	data = (ulong)&hdr;
+	len  = sizeof(image_header_t);
+	
+	checksum = ntohl(hdr.ih_hcrc);
+	hdr.ih_hcrc = 0;
+	
+	if (crc32 (0, (uchar *)data, len) != checksum) {
+		puts ("Bad Header Checksum\n");
+		return 1;
+	}
+#ifdef CONFIG_HAS_DATAFLASH
+	if (addr_dataflash(addr)){
+		len  = ntohl(hdr.ih_size) + sizeof(image_header_t);
+		read_dataflash(addr, len, (char *)CFG_LOAD_ADDR);
+		addr = CFG_LOAD_ADDR;
+	}
+#endif
+	
+	print_image_hdr ((image_header_t *)addr);
+	
+	data = addr + sizeof(image_header_t);
+	len  = ntohl(hdr.ih_size);
+	
+	puts ("   Verifying Checksum ... ");
+	if (crc32 (0, (uchar *)data, len) != ntohl(hdr.ih_dcrc)) {
+		printf ("Bad Data CRC\n");
+		return 1;
+	}
+	puts ("OK\n");
+	
+	switch (hdr.ih_comp) {
+	case IH_COMP_NONE:
+		memmove ((char *)CFG_LOAD_ADDR,(void *)data,len);
+		break;
+	case IH_COMP_GZIP:
+		if (gunzip ((char *)CFG_LOAD_ADDR,unc_len,(uchar *)data, &len) != 0) {
+			puts ("GUNZIP ERROR - FPGA not loaded\n");
+			return 1;
+		}
+		len = unc_len;
+		break;
+		
+#ifdef CONFIG_BZIP2
+	case IH_COMP_BZIP2:
+		i = BZ2_bzBuffToBuffDecompress ((char *)CFG_LOAD_ADDR,punc_len,
(char *)data, len,
+								  1, 0);
+		if (i != BZ_OK) {
+			printf ("BUNZIP2 ERROR %d - FPGA not loaded!\n", i);
+			return 1;
+		}
+		len = unc_len;
+		break;
+#endif /* CONFIG_BZIP2 */
+	default:
+		printf ("Unimplemented compression type %d\n", hdr.ih_comp);
+		return 1;
+	}
+	
+	return fpga_load(devnum,(char *)CFG_LOAD_ADDR,len);
+}

 /* Convert bitstream data and load into the fpga */
 int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
@@ -248,6 +334,10 @@
 		rc = fpga_load (dev, fpga_data, data_size);
 		break;

+	case FPGA_LOADI:
+		rc = fpga_loadi (dev, fpga_data);
+		break;
+
 	case FPGA_LOADB:
 		rc = fpga_loadbitstream(dev, fpga_data, data_size);
 		break;
@@ -298,6 +388,8 @@
 		op = FPGA_INFO;
 	} else if (!strcmp ("loadb", opstr)) {
 		op = FPGA_LOADB;
+	} else if (!strcmp ("loadi", opstr)) {
+		op = FPGA_LOADI;
 	} else if (!strcmp ("load", opstr)) {
 		op = FPGA_LOAD;
 	} else if (!strcmp ("loadmk", opstr)) {
@@ -313,12 +405,13 @@
 }

 U_BOOT_CMD (fpga, 6, 1, do_fpga,
-	    "fpga    - loadable FPGA image support\n",
-	    "fpga [operation type] [device number] [image address] [image size]\n"
-	    "fpga operations:\n"
-	    "\tinfo\tlist known device information\n"
-	    "\tload\tLoad device from memory buffer\n"
-	    "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n"
-	    "\tloadmk\tLoad device generated with mkimage\n"
-	    "\tdump\tLoad device to memory buffer\n");
+		  "fpga    - loadable FPGA image support\n",
+		  "fpga [operation type] [device number] [image address] [image size]\n"
+		  "fpga operations:\n"
+		  "\tinfo\tlist known device information\n"
+		  "\tloadi\tLoad device from u-boot image\n"
+		  "\tload\tLoad device from memory buffer\n"
+		  "\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n"
+		  "\tloadmk\tLoad device generated with mkimage\n"
+		  "\tdump\tLoad device to memory buffer\n");
 #endif /* CONFIG_FPGA && CONFIG_COMMANDS & CFG_CMD_FPGA */
=============== eof =======================

[U-Boot-Users] Altera Stratix II support

[eran liberty]

this patch correct a warining i got about const casting...
============== sof =====================
diff -x .svn -Nuar u-boot.git/common/fpga.c u-boot-exsw6000/common/fpga.c
--- u-boot.git/common/fpga.c	2007-05-28 02:11:11.000000000 +0300
+++ u-boot-exsw6000/common/fpga.c	2007-06-03 22:13:42.000000000 +0300
@@ -64,7 +64,7 @@
 /* fpga_no_sup
  * 'no support' message function
  */
-static void fpga_no_sup( char *fn, char *msg )
+static void fpga_no_sup(const char *fn,const char *msg )
 {
 	if ( fn && msg ) {
 		printf( "%s: No support for %s.  CONFIG_FPGA defined as 0x%x.\n",
@@ -207,10 +207,6 @@
 	memset( desc_table, 0, sizeof(desc_table));

 	PRINTF( "%s: CONFIG_FPGA = 0x%x\n", __FUNCTION__, CONFIG_FPGA );
-#if 0
-	PRINTF( "%s: CFG_FPGA_XILINX = 0x%x\n", __FUNCTION__, CFG_FPGA_XILINX );
-	PRINTF( "%s: CFG_FPGA_ALTERA = 0x%x\n", __FUNCTION__, CFG_FPGA_ALTERA );
-#endif
 }

 /* fpga_count
============== eof =====================

[U-Boot-Users] Altera Stratix II support

[eran liberty]

This patch adds a safety check to the cfi flash.
If the config file defined a flash smaller (maybe intentionally) then
the physical one. the cfi will read the actual size from the eprom and
will try to initialize a buffer of the wrong size... which will cause
a memory over run and unpredicted behaviour.

================ sof ===================
diff -x .svn -Nuar u-boot.git/drivers/cfi_flash.c
u-boot-exsw6000/drivers/cfi_flash.c
--- u-boot.git/drivers/cfi_flash.c 2007-05-28 02:11:11.000000000 +0300
+++ u-boot-exsw6000/drivers/cfi_flash.c 2007-06-03 22:13:42.000000000 +0300
@@ -1281,7 +1281,7 @@
erase_region_count = (tmp & 0xffff) + 1;
debug ("erase_region_count = %d erase_region_size = %d\n",
erase_region_count, erase_region_size);
- for (j = 0; j < erase_region_count; j++) {
+ for (j = 0; j < erase_region_count && sect_cnt < CFG_MAX_FLASH_SECT; j++) {
info->start[sect_cnt] = sector;
sector += (erase_region_size * size_ratio);

@@ -1323,6 +1323,9 @@
}

flash_write_cmd (info, 0, 0, info->cmd_reset);
+#if defined(CONFIG_FORCE_FLASH_BANK_SIZE)
+ info->size = CONFIG_FORCE_FLASH_BANK_SIZE;
+#endif
return (info->size);
}

================ eof ===================

[U-Boot-Users] Altera Stratix II support

[eran liberty]

This last patch will add the command bunzip2 to the u-boot shell.
allowing to uncompress a buffer in memory (or flash) into another location.
============== sof =================
diff -x .svn -Nuar u-boot.git/common/cmd_bzip2.c
u-boot-exsw6000/common/cmd_bzip2.c
--- u-boot.git/common/cmd_bzip2.c	1970-01-01 02:00:00.000000000 +0200
+++ u-boot-exsw6000/common/cmd_bzip2.c	2007-06-03 22:37:27.000000000 +0300
@@ -0,0 +1,67 @@
+/*
+ * (C) Copyright 2007
+ * Liberty Eran, Extricom, eran.liberty at gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <bzlib.h>
+
+#if defined(CONFIG_BZIP2)
+int do_bunzip2 ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong	addr, dest, count;
+	unsigned int destSize;
+	int rc;
+
+	if (argc != 4) {
+		printf ("Usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	/* Check for size specification.
+	 */
+	addr = simple_strtoul(argv[1], NULL, 16);
+	dest = simple_strtoul(argv[2], NULL, 16);
+	count = simple_strtoul(argv[3], NULL, 16);
+
+	if (count == 0) {
+		puts ("BUNZIP2 ERROR: Zero length ???\n");
+		return 1;
+	}
+
+	if ((rc = BZ2_bzBuffToBuffDecompress((char*)dest,&destSize,(char*)addr,count,1,0))
!= BZ_OK) {
+		printf ("BUNZIP2 ERROR: %d\n", rc);
+		return 1;
+	}
+	printf("BUNZIP2: decompressed image address & size: 0x%08x 0x%x
(%d)\n",dest,destSize,destSize);
+	return 0;
+
+}
+
+U_BOOT_CMD(
+	bunzip2 ,    4,    4,     do_bunzip2,
+	"bunzip2 - decompress bz2 buffers\n",
+	"src dest size_of_src\n"
+);
+#endif
+
+
diff -x .svn -Nuar u-boot.git/common/Makefile u-boot-exsw6000/common/Makefile
--- u-boot.git/common/Makefile	2007-05-28 02:11:11.000000000 +0300
+++ u-boot-exsw6000/common/Makefile	2007-06-03 22:23:57.000000000 +0300
@@ -39,7 +40,7 @@
 	  cmd_nand.o cmd_net.o cmd_nvedit.o \
 	  cmd_pci.o cmd_pcmcia.o cmd_portio.o \
 	  cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \
-	  cmd_usb.o cmd_vfd.o \
+	  cmd_usb.o cmd_vfd.o cmd_bzip2.o \
 	  command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \
 	  environment.o env_common.o \
 	  env_nand.o env_dataflash.o env_flash.o env_eeprom.o \
============== eof =================


Thats it,
Have fun,
Liberty.

[U-Boot-Users] Altera Stratix II support

[Andy Fleming]

On 6/4/07, eran liberty <eran.liberty@gmail.com> wrote:
> adds the reset register to 85xx immap

Applied

Andy

[U-Boot-Users] Altera Stratix II support

[eran liberty]

This patch adds my corp board along with an example of the Alter
Stratix board specific implementation

Alas, it is larger than 40k and will be rejected...

here is a temporary link till I will find a better place.

http://download.yousendit.com/9380CEAB68FA66F3

If anyone experience problem accessing, mail me.

Liberty

[U-Boot-Users] Altera Stratix II support

[Andy Fleming]

+/* FIXME: if tsec does not work try thorwing this in (remove the if 0)*/
+int last_stage_init(void)
+{
+	/* TSEC0 register the first phy so we dont */
+	tsec_initialize(gd->bd, 1, "2");
+	tsec_initialize(gd->bd, 2, "3");
+	tsec_initialize(gd->bd, 3, "4");
+	tsec_initialize(gd->bd, 4, "5");
+	tsec_initialize(gd->bd, 5, "6");
+	tsec_initialize(gd->bd, 6, "7");
+	tsec_initialize(gd->bd, 7, "8");
+	tsec_initialize(gd->bd, 8, "9");
+	tsec_initialize(gd->bd, 9, "10");
+	tsec_initialize(gd->bd, 10, "11");
+
+	return 0;
+}

Huh?  How can you be initializing 10 tsecs?  What part is this?

+static void cds_pci_fixup(void *blob)
+{

Um...you probably want to rename this.  Also, are you sure this is a
function you want?  This is only if your cpu is hooked up to the pci
devices through a PCI slot.

* reads a little further.  Does some math*

+	slot = 1;
+
+	for (i=0;i<len;i+=7) {
+		/* We rotate the interrupt pins so that the mapping
+		 * changes depending on the slot the carrier card is in.
+		 */
+		map[3] = ((map[3] + slot - 2) % 4) + 1;
+
+		map+=7;
+	}

Do you realize the net effect of this is nothing?  Pins 1-4 will
remain 1-4, respectively.  Delete this function altogether and (of
course) the call to it.

+#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
+#define LAWAR1 	(LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE &
LAWAR_SIZE_512M))
+
+#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
+#define LAWAR2 	(LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE &
LAWAR_SIZE_512M))

These should be CFG_PCIn_MEM_PHYS instead of CFG_PCIn_MEM_BASE.
They're defined to be the same thing, but it is the cpu-physical
address we want, not the PCI address.


+COBJS	:= $(BOARD).o \
+           ft_board.o \
+           fpga.o \
+	   ../../cds/common/eeprom.o \
+	   ../../cds/common/via.o


Um....that seems shady.  Maybe we need to move the via.c code into
drivers/  Are you sure you have a VIA chip?

 static struct tsec_info_struct tsec_info[] = {
+#if defined CONFIG_EXSW6000
+	{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
+	{2, TSEC_GIGABIT, 1},
+	{3, TSEC_GIGABIT, 2},
+	{4, TSEC_GIGABIT, 3},
+	{5, TSEC_GIGABIT, 4},
+	{6, TSEC_GIGABIT, 5},
+	{7, TSEC_GIGABIT, 6},
+	{8, TSEC_GIGABIT, 7},
+	{9, TSEC_GIGABIT, 8},
+	{10, TSEC_GIGABIT, 9},
+	{11, TSEC_GIGABIT, 10},
+#else


Are you sure about this?  You are claiming that you have 11 TSECs, and
that all of them use their own registers to access their PHY.


+#if defined(CONFIG_EXSW6000)
+	priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
+	priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR);
+#else
 	priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
 	priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
-					    tsec_info[index].phyregidx *
-					    TSEC_SIZE);
+								 tsec_info[index].phyregidx *
+								 TSEC_SIZE);
+#endif

1) Random, bad whitespace change.
2) I am *very* confused by what you did, here.  Now it looks like you
have set the phyregs back to what would happen if your phyregidx had
been 0.  And all of your TSECs share a single register set.  It looks
like you have one TSEC and 11 PHYs.  What's going on?

[U-Boot-Users] Altera Stratix II support

[eran liberty]

Most of what you have chosen to comment on is part of my new board.
some of it is still dirty work as it is all on progress and would love
to get code review on, but keep in mind its fairly young code.

On 6/6/07, Andy Fleming <afleming@gmail.com> wrote:
> +/* FIXME: if tsec does not work try thorwing this in (remove the if 0)*/
> +int last_stage_init(void)
> +{
> +       /* TSEC0 register the first phy so we dont */
> +       tsec_initialize(gd->bd, 1, "2");
> +       tsec_initialize(gd->bd, 2, "3");
> +       tsec_initialize(gd->bd, 3, "4");
> +       tsec_initialize(gd->bd, 4, "5");
> +       tsec_initialize(gd->bd, 5, "6");
> +       tsec_initialize(gd->bd, 6, "7");
> +       tsec_initialize(gd->bd, 7, "8");
> +       tsec_initialize(gd->bd, 8, "9");
> +       tsec_initialize(gd->bd, 9, "10");
> +       tsec_initialize(gd->bd, 10, "11");
> +
> +       return 0;
> +}
>
> Huh?  How can you be initializing 10 tsecs?  What part is this?
>
I can and i do. :)

> +static void cds_pci_fixup(void *blob)
> +{
>
> Um...you probably want to rename this.  Also, are you sure this is a
> function you want?  This is only if your cpu is hooked up to the pci
> devices through a PCI slot.
>
> * reads a little further.  Does some math*
>
> +       slot = 1;
> +
> +       for (i=0;i<len;i+=7) {
> +               /* We rotate the interrupt pins so that the mapping
> +                * changes depending on the slot the carrier card is in.
> +                */
> +               map[3] = ((map[3] + slot - 2) % 4) + 1;
> +
> +               map+=7;
> +       }
>
> Do you realize the net effect of this is nothing?  Pins 1-4 will
> remain 1-4, respectively.  Delete this function altogether and (of
> course) the call to it.
>
> +#define LAWBAR1 ((CFG_PCI1_MEM_BASE>>12) & 0xfffff)
> +#define LAWAR1         (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE &
> LAWAR_SIZE_512M))
> +
> +#define LAWBAR2 ((CFG_PCI2_MEM_BASE>>12) & 0xfffff)
> +#define LAWAR2         (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE &
> LAWAR_SIZE_512M))
>
> These should be CFG_PCIn_MEM_PHYS instead of CFG_PCIn_MEM_BASE.
> They're defined to be the same thing, but it is the cpu-physical
> address we want, not the PCI address.
>

this code is not mine (i have not wrote it), I will re look if i need it...

>
> +COBJS  := $(BOARD).o \
> +           ft_board.o \
> +           fpga.o \
> +          ../../cds/common/eeprom.o \
> +          ../../cds/common/via.o
>

I need to remove both eeprom.o via.o. I do not use them.. but as it is
right now, removing them breaks the build. It is in my todo list.
>
> Um....that seems shady.  Maybe we need to move the via.c code into
> drivers/  Are you sure you have a VIA chip?
>
>  static struct tsec_info_struct tsec_info[] = {
> +#if defined CONFIG_EXSW6000
> +       {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
> +       {2, TSEC_GIGABIT, 1},
> +       {3, TSEC_GIGABIT, 2},
> +       {4, TSEC_GIGABIT, 3},
> +       {5, TSEC_GIGABIT, 4},
> +       {6, TSEC_GIGABIT, 5},
> +       {7, TSEC_GIGABIT, 6},
> +       {8, TSEC_GIGABIT, 7},
> +       {9, TSEC_GIGABIT, 8},
> +       {10, TSEC_GIGABIT, 9},
> +       {11, TSEC_GIGABIT, 10},
> +#else
>

I thought i am doing something shady as well stacking all mdio on the
register of tsec0... but then i moved on to linux and saw they do
exactly the same. :)

>
> Are you sure about this?  You are claiming that you have 11 TSECs, and
> that all of them use their own registers to access their PHY.
>
>
> +#if defined(CONFIG_EXSW6000)
> +       priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR);
> +       priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR);
> +#else
>        priv->regs = (volatile tsec_t *)(TSEC_BASE_ADDR + index * TSEC_SIZE);
>        priv->phyregs = (volatile tsec_t *)(TSEC_BASE_ADDR +
> -                                           tsec_info[index].phyregidx *
> -                                           TSEC_SIZE);
> +                                                                tsec_info[index].phyregidx *
> +                                                                TSEC_SIZE);
> +#endif
>
> 1) Random, bad whitespace change.

would fix this

> 2) I am *very* confused by what you did, here.  Now it looks like you
> have set the phyregs back to what would happen if your phyregidx had
> been 0.  And all of your TSECs share a single register set.  It looks
> like you have one TSEC and 11 PHYs.  What's going on?
>

very simple. All mdio are accessed via the same registers. the one
that are in the memory space of eTSEC0

thanks for the in depth review. I appreciate the time you took to
provide these insight.

Liberty

[U-Boot-Users] Altera Stratix II support

[Andy Fleming]

On 6/6/07, eran liberty <eran.liberty@gmail.com> wrote:
> Most of what you have chosen to comment on is part of my new board.
> some of it is still dirty work as it is all on progress and would love
> to get code review on, but keep in mind its fairly young code.
>
> On 6/6/07, Andy Fleming <afleming@gmail.com> wrote:
> > +/* FIXME: if tsec does not work try thorwing this in (remove the if 0)*/
> > +int last_stage_init(void)
> > +{
> > +       /* TSEC0 register the first phy so we dont */
> > +       tsec_initialize(gd->bd, 1, "2");
> > +       tsec_initialize(gd->bd, 2, "3");
> > +       tsec_initialize(gd->bd, 3, "4");
> > +       tsec_initialize(gd->bd, 4, "5");
> > +       tsec_initialize(gd->bd, 5, "6");
> > +       tsec_initialize(gd->bd, 6, "7");
> > +       tsec_initialize(gd->bd, 7, "8");
> > +       tsec_initialize(gd->bd, 8, "9");
> > +       tsec_initialize(gd->bd, 9, "10");
> > +       tsec_initialize(gd->bd, 10, "11");
> > +
> > +       return 0;
> > +}
> >
> > Huh?  How can you be initializing 10 tsecs?  What part is this?
> >
> I can and i do. :)


I still debate that point.  The 8548 has *4* eTSECs.  Not 11.  At
best, you've created 11 virtual tsecs, each with a different PHY.
Though how you configure which one is physically connected is beyond
me.

> > +COBJS  := $(BOARD).o \
> > +           ft_board.o \
> > +           fpga.o \
> > +          ../../cds/common/eeprom.o \
> > +          ../../cds/common/via.o
> >
>
> I need to remove both eeprom.o via.o. I do not use them.. but as it is
> right now, removing them breaks the build. It is in my todo list.


Ok, good

> >  static struct tsec_info_struct tsec_info[] = {
> > +#if defined CONFIG_EXSW6000
> > +       {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
> > +       {2, TSEC_GIGABIT, 1},
> > +       {3, TSEC_GIGABIT, 2},
> > +       {4, TSEC_GIGABIT, 3},
> > +       {5, TSEC_GIGABIT, 4},
> > +       {6, TSEC_GIGABIT, 5},
> > +       {7, TSEC_GIGABIT, 6},
> > +       {8, TSEC_GIGABIT, 7},
> > +       {9, TSEC_GIGABIT, 8},
> > +       {10, TSEC_GIGABIT, 9},
> > +       {11, TSEC_GIGABIT, 10},
> > +#else
> >
>
> I thought i am doing something shady as well stacking all mdio on the
> register of tsec0... but then i moved on to linux and saw they do
> exactly the same. :)


Yes, because only tsec0's MDIO pins are exposed from the package.  The
others only connect to the internal TBI PHY, which is useful for
certain things, but that's not what you've done here.


> > 2) I am *very* confused by what you did, here.  Now it looks like you
> > have set the phyregs back to what would happen if your phyregidx had
> > been 0.  And all of your TSECs share a single register set.  It looks
> > like you have one TSEC and 11 PHYs.  What's going on?
> >
>
> very simple. All mdio are accessed via the same registers. the one
> that are in the memory space of eTSEC0


Yes, that's what phyregidx is for.  It defines which registers are
used for PHY accesses.  But you've also set up 11 tsecs all using the
same register space.  That's overkill.  It looks like you have one
tsec, and you want to be able to choose which PHY it is using by
creating one driver instances for each PHY.  So all you really need is
one driver instance, and the ability to change which PHY the tsec
configures.  That shouldn't be too  difficult.

If I'm wrong, then I'm still confused as to what the code changes to
tsec are doing.

Andy

[U-Boot-Users] Altera Stratix II support

[eran liberty]

On 6/6/07, Andy Fleming <afleming@gmail.com> wrote:
> On 6/6/07, eran liberty <eran.liberty@gmail.com> wrote:
> > Most of what you have chosen to comment on is part of my new board.
> > some of it is still dirty work as it is all on progress and would love
> > to get code review on, but keep in mind its fairly young code.
> >
> > On 6/6/07, Andy Fleming <afleming@gmail.com> wrote:
> > > +/* FIXME: if tsec does not work try thorwing this in (remove the if 0)*/
> > > +int last_stage_init(void)
> > > +{
> > > +       /* TSEC0 register the first phy so we dont */
> > > +       tsec_initialize(gd->bd, 1, "2");
> > > +       tsec_initialize(gd->bd, 2, "3");
> > > +       tsec_initialize(gd->bd, 3, "4");
> > > +       tsec_initialize(gd->bd, 4, "5");
> > > +       tsec_initialize(gd->bd, 5, "6");
> > > +       tsec_initialize(gd->bd, 6, "7");
> > > +       tsec_initialize(gd->bd, 7, "8");
> > > +       tsec_initialize(gd->bd, 8, "9");
> > > +       tsec_initialize(gd->bd, 9, "10");
> > > +       tsec_initialize(gd->bd, 10, "11");
> > > +
> > > +       return 0;
> > > +}
> > >
> > > Huh?  How can you be initializing 10 tsecs?  What part is this?
> > >
> > I can and i do. :)
>
>
> I still debate that point.  The 8548 has *4* eTSECs.  Not 11.  At
> best, you've created 11 virtual tsecs, each with a different PHY.
> Though how you configure which one is physically connected is beyond
> me.
>
> > > +COBJS  := $(BOARD).o \
> > > +           ft_board.o \
> > > +           fpga.o \
> > > +          ../../cds/common/eeprom.o \
> > > +          ../../cds/common/via.o
> > >
> >
> > I need to remove both eeprom.o via.o. I do not use them.. but as it is
> > right now, removing them breaks the build. It is in my todo list.
>
>
> Ok, good
>
> > >  static struct tsec_info_struct tsec_info[] = {
> > > +#if defined CONFIG_EXSW6000
> > > +       {TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
> > > +       {2, TSEC_GIGABIT, 1},
> > > +       {3, TSEC_GIGABIT, 2},
> > > +       {4, TSEC_GIGABIT, 3},
> > > +       {5, TSEC_GIGABIT, 4},
> > > +       {6, TSEC_GIGABIT, 5},
> > > +       {7, TSEC_GIGABIT, 6},
> > > +       {8, TSEC_GIGABIT, 7},
> > > +       {9, TSEC_GIGABIT, 8},
> > > +       {10, TSEC_GIGABIT, 9},
> > > +       {11, TSEC_GIGABIT, 10},
> > > +#else
> > >
> >
> > I thought i am doing something shady as well stacking all mdio on the
> > register of tsec0... but then i moved on to linux and saw they do
> > exactly the same. :)
>
>
> Yes, because only tsec0's MDIO pins are exposed from the package.  The
> others only connect to the internal TBI PHY, which is useful for
> certain things, but that's not what you've done here.
>
>
> > > 2) I am *very* confused by what you did, here.  Now it looks like you
> > > have set the phyregs back to what would happen if your phyregidx had
> > > been 0.  And all of your TSECs share a single register set.  It looks
> > > like you have one TSEC and 11 PHYs.  What's going on?
> > >
> >
> > very simple. All mdio are accessed via the same registers. the one
> > that are in the memory space of eTSEC0
>
>
> Yes, that's what phyregidx is for.  It defines which registers are
> used for PHY accesses.  But you've also set up 11 tsecs all using the
> same register space.  That's overkill.  It looks like you have one
> tsec, and you want to be able to choose which PHY it is using by
> creating one driver instances for each PHY.  So all you really need is
> one driver instance, and the ability to change which PHY the tsec
> configures.  That shouldn't be too  difficult.
>
> If I'm wrong, then I'm still confused as to what the code changes to
> tsec are doing.
>
> Andy
>

you are not entirely wrong... but not entirely right either.

I do have 1 Tsec which connects via phy 0.
I also have 10 more Ethernet phys which will be used by my hardware
(not Tsec), which i need to access and configure.
The slick solution was to write an my own device with miiphy_read &
write callback and not to register a complete TSEC for each one.
(indeed an over kill)

Yet, I lose nothing doing just that and got it up and running... so i
am happy with it as it is.

hope i made myself clearer.

Liberty

[U-Boot-Users] Altera Stratix II support

[David Hawkins]

> I have successfully integrated Altera Stratix II (fast passive
> parallel) into the existing FPGA framework within u-boot.

Hi Eran,

Sounds great!

I'm slammed at the moment working on hardware, so won't
get to absorb your work just yet. I notice a few comments
from Wolfgang on using the git head, and coding style
comments, so I guess you'll be working on those.

Just to refresh me, this is an 8548 with a Stratix II
configured by bit-banging I/O on the processor?
Is the FPGA on the local bus, or is it a PCI device
that U-Boot needs to configure?

Out of interest, what's the FPGA being used for?
 From your files ... extricom/exsw6000, and http://www.extricom.com,
it looks like this is a new wireless lan based product.

I've got schematics that should have been kicked out the
door months ago ... so I'll be back to those for a few
more weeks :(  As soon as I put my software-developer hat
back on I'll look in more detail at your patch, and see if
I can hack together the MPC8349E-MDS-PB and a Stratix II
kit to see if I can configure the FPGA.

Cheers
Dave