[U-Boot-Users] MPC8540, UPM Writeburst generating also read bursts

[Clemens Koller <clemens.koller@anagramm.de>]

Hello, Gerrit!

Please don't top-post and please don't remove the list. (use reply-to-all)
(and please move this thread over to linuxppc-embedded, as we are OT here)

Gerrit Van de Velde schrieb:
> Your input is appreciated. But .. I have verified the ECC, it's turned off.
> Nowadays it's configurable with CONFIG_DDR_ECC or something and I've
> used your if statement in the code to check if it was enabled but it
> was going to the else.

Fine.

> But I was just wondering, is DMA really needed to have decent
> througput? Without doing anything with DMA, we attain 500Mbit/s via
> our Gbit link from FPGA DDR memory up to a client PC. The FPGA is
> using a UPM with write/read bursts only.

You don't have single read and write instructions in your UPM?
Please post your UPM table.

> Only the other way is too
> slow at this time (upload from pc to embedded system).

Do you access the DDR memory aligned in 32byte cacheline sizes?
The UPM propably cannot burst unaligned chunks properly.
(I'm not sure about that, comments are welcome).
500MBit/s should be easy to handle with the UPM, if done right.

> I'm asking this because
> 1* I'm not a DMA expert
> 2* I must be sure that the slowness is not caused by not using DMA

1) It makes sense to use the DMA to offload the CPU for copying bulk
data if the CPU can be used for other stuff.

2) Can you first make sure that your Gbit link is working fine by copying
data from/to the CPU's memory without using the UPM?

I guess you will need to post more information about your
system (schematics, code, UPM)...

Regards,
-- 
Clemens Koller
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