[U-Boot-Users] [ARM] TI DaVinci (TMS320DM644x) support [1/5]

[U-Boot-Users] [ARM] TI DaVinci (TMS320DM644x) support [1/5]

[ksi at koi8.net]

Here it is.

Several changes from the original version:

- Got rid of types.h
- CPU directory is davinci now
- Saved something like 80 bytes in lowlevel_init.S
- Large Page NAND works now
- Removed a couple of #if 0
- MACH_TYPEs are in davinci.c now. This is wrong but nobody wants to update
   that mach-types.h header so there is no choice
- No default MAC address, having one is wrong
- A couple of harmless GCC warnings fixed
- Split in 5 text parts, no compressed patch any more
- Some other cosmetic fixes, spelling errors etc.
- Diff against the latest git tree as of right now

I do really hope it won't be sitting for another 3+ months and then declared
made against an old tree... But I'm pretty sure it is how it's going to be,
no illusions here :(

Anyway, here it goes...

Signed-off-by: Sergey Kubushyn <ksi@koi8.net>

=== Cut ===
diff -purN u-boot.git.orig/board/davinci/config.mk u-boot.git/board/davinci/config.mk
--- u-boot.git.orig/board/davinci/config.mk	1969-12-31 16:00:00.000000000 -0800
+++ u-boot.git/board/davinci/config.mk	2007-08-05 16:19:52.000000000 -0700
@@ -0,0 +1,39 @@
+#
+# (C) Copyright 2002
+# Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+# David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
+#
+# (C) Copyright 2003
+# Texas Instruments, <www.ti.com>
+# Swaminathan <swami.iyer@ti.com>
+#
+# Davinci EVM board (ARM925EJS) cpu
+# see http://www.ti.com/ for more information on Texas Instruments
+#
+# Davinci EVM has 1 bank of 256 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 9000'0000
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# Visioneering Corp. Sonata board (ARM926EJS) cpu
+#
+# Sonata board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Razorstream, LLC. SCHMOOGIE board (ARM926EJS) cpu
+#
+# Schmoogie board has 1 bank of 128 MB DDR RAM
+# Physical Address:
+# 8000'0000 to 8800'0000
+#
+# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000
+# (mem base + reserved)
+#
+# we load ourself to 8108 '0000
+#
+#
+
+# Provide at least 16MB spacing between us and the Linux Kernel image
+TEXT_BASE = 0x81080000
diff -purN u-boot.git.orig/board/davinci/davinci.c u-boot.git/board/davinci/davinci.c
--- u-boot.git.orig/board/davinci/davinci.c	1969-12-31 16:00:00.000000000 -0800
+++ u-boot.git/board/davinci/davinci.c	2007-08-05 16:19:52.000000000 -0700
@@ -0,0 +1,295 @@
+/*
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Parts are shamelessly stolen from various TI sources, original copyright
+ * follows:
+ * -----------------------------------------------------------------
+ *
+ * Copyright (C) 2004 Texas Instruments.
+ *
+ * ----------------------------------------------------------------------------
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * ----------------------------------------------------------------------------
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/emac_defs.h>
+
+#define MACH_TYPE_DAVINCI_EVM		901
+#define MACH_TYPE_SONATA		1254
+#define MACH_TYPE_SCHMOOGIE		1255
+
+extern void	i2c_init(int speed, int slaveaddr);
+extern void	timer_init(void);
+extern int	eth_hw_init(void);
+extern phy_t	phy;
+
+
+/* Works on Always On power domain only (no PD argument) */
+void lpsc_on(unsigned int id)
+{
+	dv_reg_p	mdstat, mdctl;
+
+	if (id >= DAVINCI_LPSC_GEM)
+		return;			/* Don't work on DSP Power Domain */
+
+	mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4));
+	mdctl = REG_P(PSC_MDCTL_BASE + (id * 4));
+
+	while (REG(PSC_PTSTAT) & 0x01) {;}
+
+	if ((*mdstat & 0x1f) == 0x03)
+		return;			/* Already on and enabled */
+
+	*mdctl |= 0x03;
+
+	/* Special treatment for some modules as for sprue14 p.7.4.2 */
+	if (	(id == DAVINCI_LPSC_VPSSSLV) ||
+		(id == DAVINCI_LPSC_EMAC) ||
+		(id == DAVINCI_LPSC_EMAC_WRAPPER) ||
+		(id == DAVINCI_LPSC_MDIO) ||
+		(id == DAVINCI_LPSC_USB) ||
+		(id == DAVINCI_LPSC_ATA) ||
+		(id == DAVINCI_LPSC_VLYNQ) ||
+		(id == DAVINCI_LPSC_UHPI) ||
+		(id == DAVINCI_LPSC_DDR_EMIF) ||
+		(id == DAVINCI_LPSC_AEMIF) ||
+		(id == DAVINCI_LPSC_MMC_SD) ||
+		(id == DAVINCI_LPSC_MEMSTICK) ||
+		(id == DAVINCI_LPSC_McBSP) ||
+		(id == DAVINCI_LPSC_GPIO)
+	   )
+	   	*mdctl |= 0x200;
+
+	REG(PSC_PTCMD) = 0x01;
+
+	while (REG(PSC_PTSTAT) & 0x03) {;}
+	while ((*mdstat & 0x1f) != 0x03) {;}	/* Probably an overkill... */
+}
+
+void dsp_on(void)
+{
+	int	i;
+
+	if (REG(PSC_PDSTAT1) & 0x1f)
+		return;			/* Already on */
+
+	REG(PSC_GBLCTL) |= 0x01;
+	REG(PSC_PDCTL1) |= 0x01;
+	REG(PSC_PDCTL1) &= ~0x100;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03;
+	REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff;
+	REG(PSC_PTCMD) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (REG(PSC_EPCPR) & 0x02)
+			break;
+	}
+
+	REG(PSC_CHP_SHRTSW) = 0x01;
+	REG(PSC_PDCTL1) |= 0x100;
+	REG(PSC_EPCCR) = 0x02;
+
+	for (i = 0; i < 100; i++) {
+		if (!(REG(PSC_PTSTAT) & 0x02))
+			break;
+	}
+
+	REG(PSC_GBLCTL) &= ~0x1f;
+}
+
+
+int board_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	/* arch number of the board */
+#ifdef DV_EVM
+	gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_EVM;
+#elif defined(SONATA_BOARD)
+	gd->bd->bi_arch_number = MACH_TYPE_SONATA;
+#elif defined(SCHMOOGIE)
+	gd->bd->bi_arch_number = MACH_TYPE_SCHMOOGIE;
+#else
+#error "Board is not defined in include/configs/davinci.h !!!"
+#endif
+	/* adress of boot parameters */
+	gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR;
+
+	/* Workaround for TMS320DM6446 errata 1.3.22 */
+	REG(PSC_SILVER_BULLET) = 0;
+
+	/* Power on required peripherals */
+	lpsc_on(DAVINCI_LPSC_EMAC);
+	lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+	lpsc_on(DAVINCI_LPSC_MDIO);
+	lpsc_on(DAVINCI_LPSC_I2C);
+	lpsc_on(DAVINCI_LPSC_UART0);
+	lpsc_on(DAVINCI_LPSC_TIMER1);
+	lpsc_on(DAVINCI_LPSC_GPIO);
+
+	/* Powerup the DSP */
+	dsp_on();
+
+	/* Bringup UART0 out of reset */
+	REG(UART0_PWREMU_MGMT) = 0x0000e003;
+
+	/* Enable GIO3.3V cells used for EMAC */
+	REG(VDD3P3V_PWDN) = 0;
+
+	/* Enable UART0 MUX lines */
+	REG(PINMUX1) |= 1;
+
+	/* Enable EMAC and AEMIF pins */
+	REG(PINMUX0) = 0x80000c1f;
+
+	/* Enable I2C pin Mux */
+	REG(PINMUX1) |= (1 << 7);
+
+	/* Set the Bus Priority Register to appropriate value */
+	REG(VBPR) = 0x20;
+
+	timer_init();
+
+	return(0);
+}
+
+int misc_init_r (void)
+{
+	u_int8_t	tmp[20], buf[10];
+	int		i = 0;
+	int		clk = 0;
+
+#ifdef CONFIG_HAS_UID
+	/* Set serial number from UID chip */
+#ifdef CONFIG_UID_DS28CM00
+	u_int8_t	crc_tbl[256] = {
+			0x00, 0x5e, 0xbc, 0xe2, 0x61, 0x3f, 0xdd, 0x83,
+			0xc2, 0x9c, 0x7e, 0x20, 0xa3, 0xfd, 0x1f, 0x41,
+			0x9d, 0xc3, 0x21, 0x7f, 0xfc, 0xa2, 0x40, 0x1e,
+			0x5f, 0x01, 0xe3, 0xbd, 0x3e, 0x60, 0x82, 0xdc,
+			0x23, 0x7d, 0x9f, 0xc1, 0x42, 0x1c, 0xfe, 0xa0,
+			0xe1, 0xbf, 0x5d, 0x03, 0x80, 0xde, 0x3c, 0x62,
+			0xbe, 0xe0, 0x02, 0x5c, 0xdf, 0x81, 0x63, 0x3d,
+			0x7c, 0x22, 0xc0, 0x9e, 0x1d, 0x43, 0xa1, 0xff,
+			0x46, 0x18, 0xfa, 0xa4, 0x27, 0x79, 0x9b, 0xc5,
+			0x84, 0xda, 0x38, 0x66, 0xe5, 0xbb, 0x59, 0x07,
+			0xdb, 0x85, 0x67, 0x39, 0xba, 0xe4, 0x06, 0x58,
+			0x19, 0x47, 0xa5, 0xfb, 0x78, 0x26, 0xc4, 0x9a,
+			0x65, 0x3b, 0xd9, 0x87, 0x04, 0x5a, 0xb8, 0xe6,
+			0xa7, 0xf9, 0x1b, 0x45, 0xc6, 0x98, 0x7a, 0x24,
+			0xf8, 0xa6, 0x44, 0x1a, 0x99, 0xc7, 0x25, 0x7b,
+			0x3a, 0x64, 0x86, 0xd8, 0x5b, 0x05, 0xe7, 0xb9,
+			0x8c, 0xd2, 0x30, 0x6e, 0xed, 0xb3, 0x51, 0x0f,
+			0x4e, 0x10, 0xf2, 0xac, 0x2f, 0x71, 0x93, 0xcd,
+			0x11, 0x4f, 0xad, 0xf3, 0x70, 0x2e, 0xcc, 0x92,
+			0xd3, 0x8d, 0x6f, 0x31, 0xb2, 0xec, 0x0e, 0x50,
+			0xaf, 0xf1, 0x13, 0x4d, 0xce, 0x90, 0x72, 0x2c,
+			0x6d, 0x33, 0xd1, 0x8f, 0x0c, 0x52, 0xb0, 0xee,
+			0x32, 0x6c, 0x8e, 0xd0, 0x53, 0x0d, 0xef, 0xb1,
+			0xf0, 0xae, 0x4c, 0x12, 0x91, 0xcf, 0x2d, 0x73,
+			0xca, 0x94, 0x76, 0x28, 0xab, 0xf5, 0x17, 0x49,
+			0x08, 0x56, 0xb4, 0xea, 0x69, 0x37, 0xd5, 0x8b,
+			0x57, 0x09, 0xeb, 0xb5, 0x36, 0x68, 0x8a, 0xd4,
+			0x95, 0xcb, 0x29, 0x77, 0xf4, 0xaa, 0x48, 0x16,
+			0xe9, 0xb7, 0x55, 0x0b, 0x88, 0xd6, 0x34, 0x6a,
+			0x2b, 0x75, 0x97, 0xc9, 0x4a, 0x14, 0xf6, 0xa8,
+			0x74, 0x2a, 0xc8, 0x96, 0x15, 0x4b, 0xa9, 0xf7,
+			0xb6, 0xe8, 0x0a, 0x54, 0xd7, 0x89, 0x6b, 0x35
+		};
+#endif
+#endif
+
+	clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1);
+
+	printf ("ARM Clock : %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27 ) / 2);
+	printf ("DDR Clock : %dMHz\n", (clk / 2));
+
+#if defined(DV_EVM) || defined(SONATA_BOARD)
+	/* Set Ethernet MAC address from EEPROM */
+	if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7f00, CFG_I2C_EEPROM_ADDR_LEN, buf, 6)) {
+		printf("\nEEPROM @ 0x%02x read FAILED!!!\n", CFG_I2C_EEPROM_ADDR);
+	} else {
+		tmp[0] = 0xff;
+		for (i = 0; i < 6; i++)
+			tmp[0] &= buf[i];
+
+		if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) {
+			sprintf((char *)&tmp[0], "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
+				buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+			setenv("ethaddr", (char *)&tmp[0]);
+		}
+	}
+#endif
+
+#ifdef CONFIG_HAS_UID
+	/* Set serial number from UID chip */
+#ifdef CONFIG_UID_DS28CM00
+	if (i2c_read(CFG_UID_ADDR, 0, 1, buf, 8)) {
+		printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR);
+		forceenv("serial#", "FAILED");
+	} else {
+		if (buf[0] != 0x70) {	/* Device Family Code */
+			printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR);
+			forceenv("serial#", "FAILED");
+		}
+	}
+	/* Now check CRC */
+	tmp[0] = 0;
+	for (i = 0; i < 8; i++)
+		tmp[0] = crc_tbl[tmp[0] ^ buf[i]];
+
+	if (tmp[0] != 0) {
+		printf("\nUID @ 0x%02x - BAD CRC!!!\n", CFG_UID_ADDR);
+		forceenv("serial#", "FAILED");
+	} else {
+		/* CRC OK, set "serial" env variable */
+		sprintf((char *)&tmp[0], "%02hhx%02hhx%02hhx%02hhx%02hhx%02hhx",
+			buf[6], buf[5], buf[4], buf[3], buf[2], buf[1]);
+		forceenv("serial#", (char *)&tmp[0]);
+	}
+#else
+#error "Unknown UID chip !!!"
+#endif
+#endif
+
+	if (!eth_hw_init()) {
+		printf("ethernet init failed!\n");
+	} else {
+		printf("ETH PHY   : %s\n", phy.name);
+	}
+
+#ifdef DV_EVM
+	i2c_read (0x39, 0x00, 1, (u_int8_t *)&i, 1);
+
+	setenv ("videostd", ((i  & 0x80) ? "pal" : "ntsc"));
+#endif
+
+	return (0);
+}
+
+int dram_init(void)
+{
+	DECLARE_GLOBAL_DATA_PTR;
+
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
+
+	return 0;
+}
diff -purN u-boot.git.orig/board/davinci/lowlevel_init.S u-boot.git/board/davinci/lowlevel_init.S
--- u-boot.git.orig/board/davinci/lowlevel_init.S	1969-12-31 16:00:00.000000000 -0800
+++ u-boot.git/board/davinci/lowlevel_init.S	2007-08-05 16:19:52.000000000 -0700
@@ -0,0 +1,771 @@
+/*
+ * Low-level board setup code for TI DaVinci SoC based boards.
+ *
+ * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+ *
+ * Partially based on TI sources, original copyrights follow:
+ */
+
+/*
+ * Board specific setup info
+ *
+ * (C) Copyright 2003
+ * Texas Instruments, <www.ti.com>
+ * Kshitij Gupta <Kshitij@ti.com>
+ *
+ * Modified for OMAP 1610 H2 board by Nishant Kamat, Jan 2004
+ *
+ * Modified for OMAP 5912 OSK board by Rishi Bhattacharya, Apr 2004
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Modified for DV-EVM board by Rishi Bhattacharya, Apr 2005
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * Modified for DV-EVM board by Swaminathan S, Nov 2005
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+.globl	lowlevel_init
+lowlevel_init:
+
+	/*-------------------------------------------------------*
+	 * Mask all IRQs by setting all bits in the EINT default *
+	 *-------------------------------------------------------*/
+	mov	r1, $0
+	ldr	r0, =EINT_ENABLE0
+	str	r1, [r0]
+	ldr	r0, =EINT_ENABLE1
+	str	r1, [r0]
+
+	/*------------------------------------------------------*
+	 * Put the GEM in reset					*
+	 *------------------------------------------------------*/
+
+	/* Put the GEM in reset */
+	ldr	r8, PSC_GEM_FLAG_CLEAR
+	ldr	r6, MDCTL_GEM
+	ldr	r7, [r6]
+	and	r7, r7, r8
+	str	r7, [r6]
+
+	/* Enable the Power Domain Transition Command */
+	ldr	r6, PTCMD
+	ldr	r7, [r6]
+	orr	r7, r7, $0x02
+	str	r7, [r6]
+
+	/* Check for Transition Complete(PTSTAT) */
+checkStatClkStopGem:
+	ldr	r6, PTSTAT
+	ldr	r7, [r6]
+	ands	r7, r7, $0x02
+	bne	checkStatClkStopGem
+
+	/* Check for GEM Reset Completion */
+checkGemStatClkStop:
+	ldr	r6, MDSTAT_GEM
+	ldr	r7, [r6]
+	ands	r7, r7, $0x100
+	bne	checkGemStatClkStop
+
+	/* Do this for enabling a WDT initiated reset this is a workaround
+	   for a chip bug.  Not required under normal situations */
+	ldr	r6, P1394
+	mov	r10, $0
+	str	r10, [r6]
+
+	/*------------------------------------------------------*
+	 * Enable L1 & L2 Memories in Fast mode                 *
+	 *------------------------------------------------------*/
+	ldr	r6, DFT_ENABLE
+	mov	r10, $0x01
+	str	r10, [r6]
+
+	ldr	r6, MMARG_BRF0
+	ldr	r10, MMARG_BRF0_VAL
+	str	r10, [r6]
+
+	ldr	r6, DFT_ENABLE
+	mov	r10, $0
+	str	r10, [r6]
+
+	/*------------------------------------------------------*
+	 * DDR2 PLL Initialization			    	*
+	 *------------------------------------------------------*/
+
+	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
+	mov	r10, $0
+	ldr	r6, PLL2_CTL
+	ldr	r7, PLL_CLKSRC_MASK
+	ldr	r8, [r6]
+	and	r8, r8, r7
+	mov	r9, r10, lsl $8
+	orr	r8, r8, r9
+	str	r8, [r6]
+
+	/* Select the PLLEN source */
+	ldr	r7, PLL_ENSRC_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Bypass the PLL */
+	ldr	r7, PLL_BYPASS_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
+	mov	r10, $0x20
+WaitPPL2Loop:
+	subs	r10, r10, $1
+	bne	WaitPPL2Loop
+
+	/* Reset the PLL */
+	ldr	r7, PLL_RESET_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Power up the PLL */
+	ldr	r7, PLL_PWRUP_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Enable the PLL from Disable Mode */
+	ldr	r7, PLL_DISABLE_ENABLE_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Program the PLL Multiplier */
+	ldr	r6, PLL2_PLLM
+	mov	r2, $0x17	/* 162 MHz */
+	str	r2, [r6]
+
+	/* Program the PLL2 Divisor Value */
+	ldr	r6, PLL2_DIV2
+	mov	r3, $0x01
+	str	r3, [r6]
+
+	/* Program the PLL2 Divisor Value */
+	ldr	r6, PLL2_DIV1
+	mov	r4, $0x0b	/* 54 MHz */
+	str	r4, [r6]
+
+	/* PLL2 DIV2 MMR */
+	ldr	r8, PLL2_DIV_MASK
+	ldr	r6, PLL2_DIV2
+	ldr	r9, [r6]
+	and	r8, r8, r9
+	mov	r9, $0x01
+	mov	r9, r9, lsl $15
+	orr	r8, r8, r9
+	str	r8, [r6]
+
+	/* Program the GOSET bit to take new divider values */
+	ldr	r6, PLL2_PLLCMD
+	ldr	r7, [r6]
+	orr	r7, r7, $0x01
+	str	r7, [r6]
+
+	/* Wait for Done */
+	ldr	r6, PLL2_PLLSTAT
+doneLoop_0:
+	ldr	r7, [r6]
+	ands	r7, r7, $0x01
+	bne	doneLoop_0
+
+	/* PLL2 DIV1 MMR */
+	ldr	r8, PLL2_DIV_MASK
+	ldr	r6, PLL2_DIV1
+	ldr	r9, [r6]
+	and	r8, r8, r9
+	mov	r9, $0x01
+	mov	r9, r9, lsl $15
+	orr	r8, r8, r9
+	str	r8, [r6]
+
+	/* Program the GOSET bit to take new divider values */
+	ldr	r6, PLL2_PLLCMD
+	ldr	r7, [r6]
+	orr	r7, r7, $0x01
+	str	r7, [r6]
+
+	/* Wait for Done */
+	ldr	r6, PLL2_PLLSTAT
+doneLoop:
+	ldr	r7, [r6]
+	ands	r7, r7, $0x01
+	bne	doneLoop
+
+	/* Wait for PLL to Reset Properly */
+	mov	r10, $0x218
+ResetPPL2Loop:
+	subs	r10, r10, $1
+	bne	ResetPPL2Loop
+
+	/* Bring PLL out of Reset */
+	ldr	r6, PLL2_CTL
+	ldr	r8, [r6]
+	orr	r8, r8, $0x08
+	str	r8, [r6]
+
+	/* Wait for PLL to Lock */
+	ldr	r10, PLL_LOCK_COUNT
+PLL2Lock:
+	subs	r10, r10, $1
+	bne	PLL2Lock
+
+	/* Enable the PLL */
+	ldr	r6, PLL2_CTL
+	ldr	r8, [r6]
+	orr	r8, r8, $0x01
+	str	r8, [r6]
+
+	/*------------------------------------------------------*
+	 * Issue Soft Reset to DDR Module			*
+	 *------------------------------------------------------*/
+
+	/* Shut down the DDR2 LPSC Module */
+	ldr	r8, PSC_FLAG_CLEAR
+	ldr	r6, MDCTL_DDR2
+	ldr	r7, [r6]
+	and	r7, r7, r8
+	orr	r7, r7, $0x03
+	str	r7, [r6]
+
+	/* Enable the Power Domain Transition Command */
+	ldr	r6, PTCMD
+	ldr	r7, [r6]
+	orr	r7, r7, $0x01
+	str	r7, [r6]
+
+	/* Check for Transition Complete(PTSTAT) */
+checkStatClkStop:
+	ldr	r6, PTSTAT
+	ldr	r7, [r6]
+	ands	r7, r7, $0x01
+	bne	checkStatClkStop
+
+	/* Check for DDR2 Controller Enable Completion */
+checkDDRStatClkStop:
+	ldr	r6, MDSTAT_DDR2
+	ldr	r7, [r6]
+	and	r7, r7, $0x1f
+	cmp	r7, $0x03
+	bne	checkDDRStatClkStop
+
+	/*------------------------------------------------------*
+	 * Program DDR2 MMRs for 162MHz Setting			*
+	 *------------------------------------------------------*/
+
+	/* Program PHY Control Register */
+	ldr	r6, DDRCTL
+	ldr	r7, DDRCTL_VAL
+	str	r7, [r6]
+
+	/* Program SDRAM Bank Config Register */
+	ldr	r6, SDCFG
+	ldr	r7, SDCFG_VAL
+	str	r7, [r6]
+
+	/* Program SDRAM TIM-0 Config Register */
+	ldr	r6, SDTIM0
+	ldr	r7, SDTIM0_VAL_162MHz
+	str	r7, [r6]
+
+	/* Program SDRAM TIM-1 Config Register */
+	ldr	r6, SDTIM1
+	ldr	r7, SDTIM1_VAL_162MHz
+	str	r7, [r6]
+
+	/* Program the SDRAM Bank Config Control Register */
+	ldr	r10, MASK_VAL
+	ldr	r8, SDCFG
+	ldr	r9, SDCFG_VAL
+	and	r9, r9, r10
+	str	r9, [r8]
+
+	/* Program SDRAM SDREF Config Register */
+	ldr	r6, SDREF
+	ldr	r7, SDREF_VAL
+	str	r7, [r6]
+
+	/*------------------------------------------------------*
+	 * Issue Soft Reset to DDR Module			*
+	 *------------------------------------------------------*/
+
+	/* Issue a Dummy DDR2 read/write */
+	ldr	r8, DDR2_START_ADDR
+	ldr	r7, DUMMY_VAL
+	str	r7, [r8]
+	ldr	r7, [r8]
+
+	/* Shut down the DDR2 LPSC Module */
+	ldr	r8, PSC_FLAG_CLEAR
+	ldr	r6, MDCTL_DDR2
+	ldr	r7, [r6]
+	and	r7, r7, r8
+	orr	r7, r7, $0x01
+	str	r7, [r6]
+
+	/* Enable the Power Domain Transition Command */
+	ldr	r6, PTCMD
+	ldr	r7, [r6]
+	orr	r7, r7, $0x01
+	str	r7, [r6]
+
+	/* Check for Transition Complete(PTSTAT) */
+checkStatClkStop2:
+	ldr	r6, PTSTAT
+	ldr	r7, [r6]
+	ands	r7, r7, $0x01
+	bne	checkStatClkStop2
+
+	/* Check for DDR2 Controller Enable Completion */
+checkDDRStatClkStop2:
+	ldr	r6, MDSTAT_DDR2
+	ldr	r7, [r6]
+	and	r7, r7, $0x1f
+	cmp	r7, $0x01
+	bne	checkDDRStatClkStop2
+
+	/*------------------------------------------------------*
+	 * Turn DDR2 Controller Clocks On			*
+	 *------------------------------------------------------*/
+
+	/* Enable the DDR2 LPSC Module */
+	ldr	r6, MDCTL_DDR2
+	ldr	r7, [r6]
+	orr	r7, r7, $0x03
+	str	r7, [r6]
+
+	/* Enable the Power Domain Transition Command */
+	ldr	r6, PTCMD
+	ldr	r7, [r6]
+	orr	r7, r7, $0x01
+	str	r7, [r6]
+
+	/* Check for Transition Complete(PTSTAT) */
+checkStatClkEn2:
+	ldr	r6, PTSTAT
+	ldr	r7, [r6]
+	ands	r7, r7, $0x01
+	bne	checkStatClkEn2
+
+	/* Check for DDR2 Controller Enable Completion */
+checkDDRStatClkEn2:
+	ldr	r6, MDSTAT_DDR2
+	ldr	r7, [r6]
+	and	r7, r7, $0x1f
+	cmp	r7, $0x03
+	bne	checkDDRStatClkEn2
+
+	/*  DDR Writes and Reads */
+	ldr	r6, CFGTEST
+	mov	r3, $0x01
+	str	r3, [r6]
+
+	/*------------------------------------------------------*
+	 * System PLL Initialization				*
+	 *------------------------------------------------------*/
+
+	/* Select the Clock Mode Depending on the Value written in the Boot Table by the run script */
+	mov	r2, $0
+	ldr	r6, PLL1_CTL
+	ldr	r7, PLL_CLKSRC_MASK
+	ldr	r8, [r6]
+	and	r8, r8, r7
+	mov	r9, r2, lsl $8
+	orr	r8, r8, r9
+	str	r8, [r6]
+
+	/* Select the PLLEN source */
+	ldr	r7, PLL_ENSRC_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Bypass the PLL */
+	ldr	r7, PLL_BYPASS_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Wait for few cycles to allow PLLEN Mux switch properly to bypass Clock */
+	mov	r10, $0x20
+
+WaitLoop:
+	subs	r10, r10, $1
+	bne	WaitLoop
+
+	/* Reset the PLL */
+	ldr	r7, PLL_RESET_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Disable the PLL */
+	orr	r8, r8, $0x10
+	str	r8, [r6]
+
+	/* Power up the PLL */
+	ldr	r7, PLL_PWRUP_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Enable the PLL from Disable Mode */
+	ldr	r7, PLL_DISABLE_ENABLE_MASK
+	and	r8, r8, r7
+	str	r8, [r6]
+
+	/* Program the PLL Multiplier */
+	ldr	r6, PLL1_PLLM
+	mov	r3, $0x15	/* For 594MHz */
+	str	r3, [r6]
+
+	/* Wait for PLL to Reset Properly */
+	mov	r10, $0xff
+
+ResetLoop:
+	subs	r10, r10, $1
+	bne	ResetLoop
+
+	/* Bring PLL out of Reset */
+	ldr	r6, PLL1_CTL
+	orr	r8, r8, $0x08
+	str	r8, [r6]
+
+	/* Wait for PLL to Lock */
+	ldr	r10, PLL_LOCK_COUNT
+
+PLL1Lock:
+	subs	r10, r10, $1
+	bne	PLL1Lock
+
+	/* Enable the PLL */
+	orr	r8, r8, $0x01
+	str	r8, [r6]
+
+	nop
+	nop
+	nop
+	nop
+
+	/*------------------------------------------------------*
+	 * AEMIF configuration for NOR Flash (double check)     *
+	 *------------------------------------------------------*/
+	ldr	r0, _PINMUX0
+	ldr	r1, _DEV_SETTING
+	str	r1, [r0]
+
+	ldr	r0, WAITCFG
+	ldr	r1, WAITCFG_VAL
+	ldr	r2, [r0]
+	orr	r2, r2, r1
+	str	r2, [r0]
+
+	ldr	r0, ACFG3
+	ldr	r1, ACFG3_VAL
+	ldr	r2, [r0]
+	and	r1, r2, r1
+	str	r1, [r0]
+
+	ldr	r0, ACFG4
+	ldr	r1, ACFG4_VAL
+	ldr	r2, [r0]
+	and	r1, r2, r1
+	str	r1, [r0]
+
+	ldr	r0, ACFG5
+	ldr	r1, ACFG5_VAL
+	ldr	r2, [r0]
+	and	r1, r2, r1
+	str	r1, [r0]
+
+	/*--------------------------------------*
+	 * VTP manual Calibration               *
+	 *--------------------------------------*/
+	ldr	r0, VTPIOCR
+	ldr	r1, VTP_MMR0
+	str	r1, [r0]
+
+	ldr	r0, VTPIOCR
+	ldr	r1, VTP_MMR1
+	str	r1, [r0]
+
+	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
+	ldr	r10, VTP_LOCK_COUNT
+VTPLock:
+	subs	r10, r10, $1
+	bne	VTPLock
+
+	ldr	r6, DFT_ENABLE
+	mov	r10, $0x01
+	str	r10, [r6]
+
+	ldr	r6, DDRVTPR
+	ldr	r7, [r6]
+	and	r7, r7, $0x1f
+	and	r8, r7, $0x3e0
+	orr	r8, r7, r8
+	ldr	r7, VTP_RECAL
+	orr	r8, r7, r8
+	ldr	r7, VTP_EN
+	orr	r8, r7, r8
+	str	r8, [r0]
+
+
+	/* Wait for 33 VTP CLK cycles.  VRP operates at 27 MHz */
+	ldr	r10, VTP_LOCK_COUNT
+VTP1Lock:
+	subs	r10, r10, $1
+	bne	VTP1Lock
+
+	ldr	r1, [r0]
+	ldr	r2, VTP_MASK
+	and	r2, r1, r2
+	str	r2, [r0]
+
+	ldr	r6, DFT_ENABLE
+	mov	r10, $0
+	str	r10, [r6]
+
+#ifdef SONATA_BOARD_GPIOWP
+	/* Set PINMUX0 to enable GPIO4 */
+	ldr	r0, _PINMUX0
+	ldr	r1, GPIO4_EN_MASK
+	ldr	r2, [r0]
+	and	r2, r2, r1
+	str	r2, [r0]
+
+	/* Enable GPIO LPSC module */
+	ldr	r0, PTSTAT
+
+gpio_ptstat_loop1:
+	ldr	r2, [r0]
+	tst	r2, $0x00000001
+	bne	gpio_ptstat_loop1
+
+	ldr	r1, MDCTL_GPIO
+	ldr	r2, [r1]
+	and	r2, r2, $0xfffffff8
+	orr	r2, r2, $0x00000003
+	str	r2, [r1]
+
+	orr	r2, r2, $0x00000200
+	str	r2, [r1]
+
+	ldr	r1, PTCMD
+	mov	r2, $0x00000001
+	str	r2, [r1]
+
+gpio_ptstat_loop2:
+	ldr	r2, [r0]
+	tst	r2, $0x00000001
+	bne	gpio_ptstat_loop2
+
+	ldr	r0, MDSTAT_GPIO
+gpio_mdstat_loop:
+	ldr	r2, [r0]
+	and	r2, r2, $0x0000001f
+	teq	r2, $0x00000003
+	bne	gpio_mdstat_loop
+
+	/* GPIO4 -> output */
+	ldr	r0, GPIO_DIR01
+	mov	r1, $0x10
+	ldr	r2, [r0]
+	bic	r2, r2, r0
+	str	r2, [r0]
+
+	/* Set it to 0 (Write Protect) */
+	ldr	r0, GPIO_CLR_DATA01
+	str	r1, [r0]
+#endif
+
+	/* back to arch calling code */
+	mov	pc, lr
+
+.ltorg
+
+_PINMUX0:
+	.word	0x01c40000		/* Device Configuration Registers */
+_PINMUX1:
+	.word	0x01c40004		/* Device Configuration Registers */
+
+_DEV_SETTING:
+	.word	0x00000c1f
+
+#ifdef SONATA_BOARD_GPIOWP
+GPIO4_EN_MASK:
+	.word	0xf77fffff
+MDCTL_GPIO:
+	.word	0x01c41a68
+MDSTAT_GPIO:
+	.word	0x01c41868
+GPIO_DIR01:
+	.word	0x01c67010
+GPIO_SET_DATA01:
+	.word	0x01c67018
+GPIO_CLR_DATA01:
+	.word	0x01c6701c
+#endif
+
+WAITCFG:
+	.word	0x01e00004
+WAITCFG_VAL:
+	.word	0
+ACFG3:
+	.word	0x01e00014
+ACFG3_VAL:
+	.word	0x3ffffffd
+ACFG4:
+	.word	0x01e00018
+ACFG4_VAL:
+	.word	0x3ffffffd
+ACFG5:
+	.word	0x01e0001c
+ACFG5_VAL:
+	.word	0x3ffffffd
+
+MDCTL_DDR2:
+	.word	0x01c41a34
+MDSTAT_DDR2:
+	.word	0x01c41834
+
+PTCMD:
+	.word	0x01c41120
+PTSTAT:
+	.word	0x01c41128
+
+EINT_ENABLE0:
+	.word	0x01c48018
+EINT_ENABLE1:
+	.word	0x01c4801c
+
+PSC_FLAG_CLEAR:
+	.word	0xffffffe0
+PSC_GEM_FLAG_CLEAR:
+	.word	0xfffffeff
+
+/* DDR2 MMR & CONFIGURATION VALUES, 162 MHZ clock */
+DDRCTL:
+	.word	0x200000e4
+DDRCTL_VAL:
+	.word	0x50006405
+SDREF:
+	.word	0x2000000c
+SDREF_VAL:
+	.word	0x000005c3
+SDCFG:
+	.word	0x20000008
+SDCFG_VAL:
+#ifdef	DDR_4BANKS
+	.word	0x00178622
+#elif defined DDR_8BANKS
+	.word	0x00178632
+#else
+#error "Unknown DDR configuration!!!"
+#endif
+SDTIM0:
+	.word	0x20000010
+SDTIM0_VAL_162MHz:
+	.word	0x28923211
+SDTIM1:
+	.word	0x20000014
+SDTIM1_VAL_162MHz:
+	.word	0x0016c722
+VTPIOCR:
+	.word	0x200000f0	/* VTP IO Control register */
+DDRVTPR:
+	.word	0x01c42030	/* DDR VPTR MMR */
+VTP_MMR0:
+	.word	0x201f
+VTP_MMR1:
+	.word	0xa01f
+DFT_ENABLE:
+	.word	0x01c4004c
+VTP_LOCK_COUNT:
+	.word	0x5b0
+VTP_MASK:
+	.word	0xffffdfff
+VTP_RECAL:
+	.word	0x40000
+VTP_EN:
+	.word	0x02000
+CFGTEST:
+	.word	0x80010000
+MASK_VAL:
+	.word	0x00000fff
+
+/* GEM Power Up & LPSC Control Register */
+MDCTL_GEM:
+	.word	0x01c41a9c
+MDSTAT_GEM:
+	.word	0x01c4189c
+
+/* For WDT reset chip bug */
+P1394:
+	.word	0x01c41a20
+
+PLL_CLKSRC_MASK:
+	.word	0xfffffeff	/* Mask the Clock Mode bit */
+PLL_ENSRC_MASK:
+	.word	0xffffffdf	/* Select the PLLEN source */
+PLL_BYPASS_MASK:
+	.word	0xfffffffe	/* Put the PLL in BYPASS */
+PLL_RESET_MASK:
+	.word	0xfffffff7	/* Put the PLL in Reset Mode */
+PLL_PWRUP_MASK:
+	.word	0xfffffffd	/* PLL Power up Mask Bit  */
+PLL_DISABLE_ENABLE_MASK:
+	.word	0xffffffef	/* Enable the PLL from Disable */
+PLL_LOCK_COUNT:
+	.word	0x2000
+
+/* PLL1-SYSTEM PLL MMRs */
+PLL1_CTL:
+	.word	0x01c40900
+PLL1_PLLM:
+	.word	0x01c40910
+
+/* PLL2-SYSTEM PLL MMRs */
+PLL2_CTL:
+	.word	0x01c40d00
+PLL2_PLLM:
+	.word	0x01c40d10
+PLL2_DIV1:
+	.word	0x01c40d18
+PLL2_DIV2:
+	.word	0x01c40d1c
+PLL2_PLLCMD:
+	.word	0x01c40d38
+PLL2_PLLSTAT:
+	.word	0x01c40d3c
+PLL2_DIV_MASK:
+	.word	0xffff7fff
+
+MMARG_BRF0:
+	.word	0x01c42010	/* BRF margin mode 0 (R/W)*/
+MMARG_BRF0_VAL:
+	.word	0x00444400
+
+DDR2_START_ADDR:
+	.word	0x80000000
+DUMMY_VAL:
+	.word	0xa55aa55a
diff -purN u-boot.git.orig/board/davinci/Makefile u-boot.git/board/davinci/Makefile
--- u-boot.git.orig/board/davinci/Makefile	1969-12-31 16:00:00.000000000 -0800
+++ u-boot.git/board/davinci/Makefile	2007-08-05 16:19:52.000000000 -0700
@@ -0,0 +1,52 @@
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd at denx.de.
+#
+# Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS	:= davinci.o nand.o
+SOBJS	:= lowlevel_init.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak *~ .depend
+
+#########################################################################
+# This is for $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff -purN u-boot.git.orig/board/davinci/u-boot.lds u-boot.git/board/davinci/u-boot.lds
--- u-boot.git.orig/board/davinci/u-boot.lds	1969-12-31 16:00:00.000000000 -0800
+++ u-boot.git/board/davinci/u-boot.lds	2007-08-05 16:19:52.000000000 -0700
@@ -0,0 +1,52 @@
+/*
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+	. = ALIGN(4);
+	.text	:
+	{
+	  cpu/arm926ejs/start.o	(.text)
+	  *(.text)
+	}
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+	. = ALIGN(4);
+	.data : { *(.data) }
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.u_boot_cmd : { *(.u_boot_cmd) }
+	__u_boot_cmd_end = .;
+
+	. = ALIGN(4);
+	__bss_start = .;
+	.bss : { *(.bss) }
+	_end = .;
+}
=== Cut ===

---
******************************************************************
*  KSI at home    KOI8 Net  < >  The impossible we do immediately.  *
*  Las Vegas   NV, USA   < >  Miracles require 24-hour notice.   *
******************************************************************

[U-Boot-Users] [ARM] TI DaVinci (TMS320DM644x) support [1/5]

[Stefan Roese]

Hi Sergey,

On Monday 06 August 2007, ksi at koi8.net wrote:
> Here it is.
>
> Several changes from the original version:
>
> - Got rid of types.h
> - CPU directory is davinci now
> - Saved something like 80 bytes in lowlevel_init.S
> - Large Page NAND works now
> - Removed a couple of #if 0
> - MACH_TYPEs are in davinci.c now. This is wrong but nobody wants to update
>    that mach-types.h header so there is no choice
> - No default MAC address, having one is wrong
> - A couple of harmless GCC warnings fixed
> - Split in 5 text parts, no compressed patch any more
> - Some other cosmetic fixes, spelling errors etc.
> - Diff against the latest git tree as of right now
>
> I do really hope it won't be sitting for another 3+ months and then
> declared made against an old tree... But I'm pretty sure it is how it's
> going to be, no illusions here :(

Hopefully you will be proven wrong here. Thanks for all the rework.

Seems that we now have two versions of the DaVinci patches. I suggest to use 
your patches for inclusion instead of Dirk's, because you are the original 
author. Dirk is welcome to send some review comments and/or 
Acked-by/Signed-off-by lines of course.

Here one comments from myself (I have to admit that the inline patches make 
the review a lot easier for me, since I'm sometimes just to lazy do it with 
attached compressed patches ;)):

I noticed that you have one board directory "board/davinci". And from my 
understanding (I'm no DaVinci expert at all) a lot of CPU (SoC) code is 
included in this board directory. Stuff like nand-driver or lowlevel_init 
seem quite cpu-specific. Please correct me if I'm wrong here. But if my 
finding is correct, I would like to seem some of this cpu-specific stuff 
moved into the cpu directory and perhaps rename the board directory into 
something not that generic as "board/davinci". We usually name the board 
directory according to the name of the board itself. You are supporting 3 
different boards in this board directory right now. This makes it difficult 
to pick a name for such a board directory. But when more and more DaVince 
port will emerge, it will not be possible anymore to support them all in one 
board directory. It should be one board directory per board. Only *very* 
similar board should share a board directory.

So I suggest to create 3 separate board directories and try to move the 
generic, cpu-specific stuff in the cpu directory.

What do you think? Does this make sense?

Thanks.

Best regards,
Stefan

=====================================================================
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office at denx.de
=====================================================================

[U-Boot-Users] [ARM] TI DaVinci (TMS320DM644x) support [1/5]

[Philip Balister]

Stefan Roese wrote:
> I noticed that you have one board directory "board/davinci". And from my 
> understanding (I'm no DaVinci expert at all) a lot of CPU (SoC) code is 
> included in this board directory. Stuff like nand-driver or lowlevel_init 
> seem quite cpu-specific. Please correct me if I'm wrong here. But if my 
> finding is correct, I would like to seem some of this cpu-specific stuff 
> moved into the cpu directory and perhaps rename the board directory into 
> something not that generic as "board/davinci". We usually name the board 
> directory according to the name of the board itself. You are supporting 3 
> different boards in this board directory right now. This makes it difficult 
> to pick a name for such a board directory. But when more and more DaVince 
> port will emerge, it will not be possible anymore to support them all in one 
> board directory. It should be one board directory per board. Only *very* 
> similar board should share a board directory.
> 
> So I suggest to create 3 separate board directories and try to move the 
> generic, cpu-specific stuff in the cpu directory.
> 
> What do you think? Does this make sense?

I agree with Stefan. Although different boards using a davinci 
processor, in the case a dm6446 ..., are similar, trying to capture 
board differences in one common uboot board directory makes the addition 
of new boards very difficult. The config/davinci.h in Sergey's latest 
patch requires you set a #define for your board and then makes all 
selections of config options based on this #define. I have tried adding 
a new board hos patches and gave up when I kept losing track of where I 
was in sets of nested #ifdef's.

I think Dirk did a good job trying to break up Sergey's work into 
patches for review. The key thing to move forward is get a set of 
patches accepted into uboot git so davinci users can start testing and 
adding support for their own boards. Once we get the first patches in, I 
think the process will go much smoother.

Philip

PS: I am not a uboot guru, but the people I work with think I am.
-------------- next part --------------
A non-text attachment was scrubbed...
Name: smime.p7s
Type: application/x-pkcs7-signature
Size: 3303 bytes
Desc: S/MIME Cryptographic Signature
Url : http://lists.denx.de/pipermail/u-boot/attachments/20070806/15b62a97/attachment.bin 

[U-Boot-Users] [ARM] TI DaVinci (TMS320DM644x) support [1/5]

[Dirk Behme]

Stefan Roese wrote:
> Hi Sergey,
> 
> On Monday 06 August 2007, ksi at koi8.net wrote:
> 
>>Here it is.
>>
>>Several changes from the original version:
>>
>>- Got rid of types.h
>>- CPU directory is davinci now
>>- Saved something like 80 bytes in lowlevel_init.S
>>- Large Page NAND works now
>>- Removed a couple of #if 0
>>- MACH_TYPEs are in davinci.c now. This is wrong but nobody wants to update
>>   that mach-types.h header so there is no choice
>>- No default MAC address, having one is wrong
>>- A couple of harmless GCC warnings fixed
>>- Split in 5 text parts, no compressed patch any more
>>- Some other cosmetic fixes, spelling errors etc.
>>- Diff against the latest git tree as of right now
>>
>>I do really hope it won't be sitting for another 3+ months and then
>>declared made against an old tree... But I'm pretty sure it is how it's
>>going to be, no illusions here :(
> 
> 
> Hopefully you will be proven wrong here. Thanks for all the rework.
> 
> Seems that we now have two versions of the DaVinci patches. I suggest to use 
> your patches for inclusion instead of Dirk's, because you are the original 
> author.

Yes, that's okay. If I helped a little to get the patches updated, 
that's fine for me.

> Dirk is welcome to send some review comments and/or 
> Acked-by/Signed-off-by lines of course.

I will do this.

Best regards

Dirk

[U-Boot-Users] [ARM] TI DaVinci (TMS320DM644x) support [1/5]

[ksi at koi8.net]

On Mon, 6 Aug 2007, Philip Balister wrote:

OK, I'm splitting them up. As a matter of fact there is little
board-specific code, almost everything should go into CPU directory.

Will post a new set later today.

> Stefan Roese wrote:
>> I noticed that you have one board directory "board/davinci". And from
> my 
>> understanding (I'm no DaVinci expert at all) a lot of CPU (SoC) code
> is 
>> included in this board directory. Stuff like nand-driver or
> lowlevel_init 
>> seem quite cpu-specific. Please correct me if I'm wrong here. But if
> my 
>> finding is correct, I would like to seem some of this cpu-specific
> stuff 
>> moved into the cpu directory and perhaps rename the board directory
> into 
>> something not that generic as "board/davinci". We usually name the
> board 
>> directory according to the name of the board itself. You are
> supporting 3 
>> different boards in this board directory right now. This makes it
> difficult 
>> to pick a name for such a board directory. But when more and more
> DaVince 
>> port will emerge, it will not be possible anymore to support them all
> in 
>> one board directory. It should be one board directory per board. Only 
>> *very* similar board should share a board directory.
>> 
>> So I suggest to create 3 separate board directories and try to move
> the 
>> generic, cpu-specific stuff in the cpu directory.
>> 
>> What do you think? Does this make sense?
>
> I agree with Stefan. Although different boards using a davinci
> processor, in 
> the case a dm6446 ..., are similar, trying to capture board differences
> in 
> one common uboot board directory makes the addition of new boards very 
> difficult. The config/davinci.h in Sergey's latest patch requires you
> set a 
> #define for your board and then makes all selections of config options
> based 
> on this #define. I have tried adding a new board hos patches and gave up
> when 
> I kept losing track of where I was in sets of nested #ifdef's.
>
> I think Dirk did a good job trying to break up Sergey's work into
> patches for 
> review. The key thing to move forward is get a set of patches accepted
> into 
> uboot git so davinci users can start testing and adding support for
> their own 
> boards. Once we get the first patches in, I think the process will go
> much 
> smoother.
>
> Philip
>
> PS: I am not a uboot guru, but the people I work with think I am.
>

---
******************************************************************
*  KSI at home    KOI8 Net  < >  The impossible we do immediately.  *
*  Las Vegas   NV, USA   < >  Miracles require 24-hour notice.   *
******************************************************************