[U-Boot-Users] Device tree question for 85xx

[Scott Wood <scottwood@freescale.com>]

robert lazarski wrote:
> Hi all, please excuse if device tree questions are off topic for this
> list - I already tried linuxppc-embedded2 on usenet with no luck. I've
> also been reading booting-without-of.txt .

I'm not familiar with "linuxppc-embedded2", but 
linuxppc-embedded at ozlabs.org is the place for this kind of thing.

> I'm trying to define the 'mdio' and 'ethernet' nodes for my mpc8548e
> board that arrives soon, using cds for my reference. The cds reference
> has a Quad PHY of either a CIS8204 or a 88E1145 - swappable as a
> mezzanine I believe. Our board has two dual PHY's - 88E1111 and a
> 88E1121R . Our hardware engineer has simply defined four external
> interrupts:
> 
> IRQ0 : PHY 0 - TSEC 1 (P0 of the 88E1121R)
> IRQ1 : PHY 1 - TSEC 2 (P1 of the 88E1121R)
> IRQ2 : PHY 2 - TSEC 3 (88E1111)
> IRQ3 : PHY 3 - TSEC 4 (88E1111)
> 
> The docs say the interrupts depend on the 'type of interrupt
> controller' - which is on chip I believe for the 8548.  Here's how cds
> has it in the linux-2.6.22/arch/powerpc/boot/dts/mpc8548cds.dts - Can
> anyone please help me understand how to define a dts for my board?
> I've been struggling to understand how this works - any help
> appreciated.


External interrupts start at zero (internal interrupt numbers have 0x10 
added to them), so the first cell should correspond to the external IRQ 
number.

The second cell encodes the level and sense information, and is 
documented in Documentation/powerpc/booting-without-of.txt:

         0 = low to high edge sensitive type enabled
         1 = active low level sensitive type enabled
         2 = active high level sensitive type enabled
         3 = high to low edge sensitive type enabled
 

-Scott