[U-Boot-Users] BDI2000 problems flashing virgin custom 8548 board

[Ben Warren <bwarren@qstreams.com>]

robert lazarski wrote:
> On 8/30/07, Ben Warren <bwarren@qstreams.com> wrote:
>   
>> One other thing I just thought of - you need to make sure the Local Bus
>> Access Windows are set properly. My chip has separate ones for DDR and
>> for Local Bus, and yours may as well. The config file you sent has the
>> LAWBAR for local bus set to 0x000c0000, when it should be 0xf8000000, I
>> think. If this is set wrong, I don't think you'll be able to access the
>> memory range. Info is in the 'System Configuration' section of your
>> reference manual.
>>
>>     
>
> Which manual? I tried
>
>   
The reference manual for your CPU. Probably has a Freescale part number 
of MPC8548ERM or something like that.
> This part I'm having problems understanding. This is what I have for
> the config of MPC8548CDS board - what I'm using as a reference:
>
> ; Initialize LAWBAR's
> WM32    0xe0000C08      0x00000000      ;LAWBAR0 : @0x00000000
> WM32    0xe0000C10      0x80f0001b      ;LAWAR0  : DDR/SDRAM  256MB
> WM32    0xe0000C28      0x000c0000      ;LAWBAR1 : @0xc0000000
> WM32    0xe0000C30      0x8040001d      ;LAWAR1  : Local Bus  1GB
>
> In what manual is this explained in, ie the 0xe0000 addresses? I can't
> seem to tie together the LAW's in my init.S and the LAW's here.
>
>   
All internal registers are mapped according to a register named IMMRBAR, 
which typically is set to 0xe0000000 by the CPU bootstrap process, which 
is dictated by some other registers called Reset Configuration Words. So 
anything you see that begins with 0xe0000000 is an internal register. 
There's a chapter of the reference manual called, fittingly enough, 
'Memory Map', that outlines all of these registers and cross references 
to other parts of the manual. The addresses shown in the memory map 
table are offsets from IMMRBAR. Confused yet?
> /*
>  * LAW(Local Access Window) configuration:
>  *
>  * 0x0000_0000     0x7fff_ffff     DDR                     2G
>  * 0x8000_0000     0x9fff_ffff     PCI1 MEM                512M
>  * 0xa000_0000     0xbfff_ffff     PCIe MEM                512M
>  * 0xc000_0000     0xdfff_ffff     PCI2 MEM                512M
>  * 0xe000_0000     0xe000_ffff     CCSR                    1M
>  * 0xe200_0000     0xe10f_ffff     PCI1 IO                 1M
>  * 0xe280_0000     0xe20f_ffff     PCI2 IO                 1M
>  * 0xe300_0000     0xe30f_ffff     PCIe IO                 1M
>  * 0xf800_0000     0xffff_ffff     FLASH (boot bank)       128M
>  *
>   
Looks like a nice memory partition according to function. You can see 
here that 1MB starting at 0xe0000000 is reserved for internal registers, 
and everything else is allocated for memory and busses.
>  * Notes:
>  *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
>  *    If flash is 8M at default position (last 8M), no LAW needed.
>  *
>  * LAW 0 is reserved for boot mapping
>  */
>
>   
At initial bootup, things are a bit different. Since the CPU has no 
inherent knowledge of what type of boot device you have, it initializes 
Chip Select 0 to the entire 4GB range, and likely LAW0 as well. That's 
probably what this refers to. Once you start hitting things with your 
BDI-2000 INIT section, this no longer applies.


I recommend you set LAW0 to cover 0xf8000000 to 0xffffffff (your 128MB 
flash) and don't set any of the other access windows. This should at 
least let you access the flash chip.

Well, that's enough fun for one day. Time to go home.

cheers,
Ben