[U-Boot-Users] minimum bdi config to read flash on 85xx

[Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>]

David Hawkins wrote:
> Hi Robert,
> 
>> OK guys I have a sense of humour
> 
> Its a pre-requisite; that, and tough skin ;)

[snip]

>> Beyond that the magic numbers are for the first and second
>> unlock cycles and for autoselect, we cannot understand why
>> bdi configs use 0x0600 and 0x00d0 for their magic
>> numbers - which are not the same magic numbers in the
>> manuals best as we can tell.
> 
> It depends on how the Flash is wired. As far as data
> wires go, Flash[15:0] can connect to Processor[15:0]
> or Processor[0:15]. Whatever the processor writes,
> it'll read back.
> 
> However, the Flash command codes expect the bit pattern
> as defined in the command codes table on Flash[15:0].
> 
> So you've got lots of board specific cases;
> 
>   * bits reversed
>   * bytes swapped
>   * bits in bytes reversed
> 
> and so on ...
> 
> If the command code was 0x0006, and the BDI config you
> copied shows 0x0600, then they've got bytes swapped.
> If the code was 0x0060, and the bus is reversed
> then you'll get 0x0600.
> 
> When you copy someone elses design without understanding
> it, you can end up copying their mistakes.
> 
> In your case, you hooked up your Flash correctly, but
> you're trying to interpret someone else's design in
> the context of your design.
> 
> Rather than that, just look at the data sheets and
> your specific design. You've gained an understanding
> of what the BDI configuration file should contain,
> now toss away anyone elses configs ... or look at them
> with a 'grain of salt'.
> 
> Cheers,
> Dave

I have limited CFI experience, but my flash experience is that the flash 
chips ignore extra bytes in the data lanes when you send commands. 
Assuming your flash isn't bit-swapped, you should be able to write the 
magic bytes down all four byte lanes and have it work for byte-wide, 
16-bit-wide, and 32-bit-wide chips or paralleled 8-bit or 16-bit wide 
chips.  This neatly solves the byte swap issue as well.

The other critical part is the address you use.  Depending on the width 
of your chip(s) and if more than one paralleled on the bus, you will 
have to add zero "0" bits to the magic 55 / AA addresses in the manual.

For the translation of byte-wide to 16 bit wide:
55 (0101_0101) becomes 0AA (0_1010_1010)
AA (1010_1010) becomes 254 (1_0101_0100)
                                       ^ added '0' bit

For the translation of byte-wide to 32 bit wide:
55 (0101_0101) becomes 154 (01_0101_0100)
AA (1010_1010) becomes 2A8 (10_1010_1000)
                                       ^^ two added '0' bits

Best regards,
gvb