[U-Boot-Users] minimum bdi config to read flash on 85xx

[David Hawkins <dwh@ovro.caltech.edu>]

Hi Jerry,

> I have limited CFI experience, but my flash experience is that the flash 
> chips ignore extra bytes in the data lanes when you send commands. 
> Assuming your flash isn't bit-swapped, you should be able to write the 
> magic bytes down all four byte lanes and have it work for byte-wide, 
> 16-bit-wide, and 32-bit-wide chips or paralleled 8-bit or 16-bit wide 
> chips.  This neatly solves the byte swap issue as well.

Nice to know, thanks.

> The other critical part is the address you use.  Depending on the width 
> of your chip(s) and if more than one paralleled on the bus, you will 
> have to add zero "0" bits to the magic 55 / AA addresses in the manual.
> 
> For the translation of byte-wide to 16 bit wide:
> 55 (0101_0101) becomes 0AA (0_1010_1010)
> AA (1010_1010) becomes 254 (1_0101_0100)
>                                       ^ added '0' bit
> 
> For the translation of byte-wide to 32 bit wide:
> 55 (0101_0101) becomes 154 (01_0101_0100)
> AA (1010_1010) becomes 2A8 (10_1010_1000)
>                                       ^^ two added '0' bits

Ooh, thats a sneaky one.

I think (hope) the Spansion chips are 'smarter' than that.
They have a BYTE# pin that configures it to operate
in 8-bit (low) versus 16-bit (high), and in byte mode
DQ15 become A-1 (address bit minus -1). I'm pretty sure
the Spansion data sheet describes the commands in terms
of byte addresses, so there is no ambiguity of byte
versus 'word' (which has so many meanings ...) addresses
in the command codes.

Robert has correctly connected the Flash address and data
signals, so he shouldn't have to massage the address/data
relative to the data sheet command codes.

I'm pretty sure the Altera FPGA boards that I ran some tests
on used Spansion Flash, and I didn't have to shift the
address part of the Flash command.

Nice info though, thanks.
Dave